View NT5CB64M16AP-CF_6941963.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 1 rev 1 . 2 0 1 / 200 9 feature ? 1. 5 v 0. 75 v (jedec standard power supply ) ? 8 i nternal memory banks (ba0 - ba2) ? differential clock input (ck, ?? ) ? programmable ??? latency: 5, 6, 7, 8, 9 ? programmable additive latency: 0 , cl - 1, cl - 2 ? programmable sequential / interleave burst type ? programmable burst length: 4, 8 ? 8 bit prefetch architecture ? output driver impedance control ? w r ite leveling ? ocd calibration ? dynamic odt ( rtt_nom & rtt_wr) ? auto self - refresh ? self - refresh temperature ? partial array self - refresh ? rohs compliance ? packages: 60 - ball bga for x8 components 84 - ball bga for x16 components description the 1gb double - data - rate - 3 (ddr 3 ) drams is a h igh - speed cmos double data rate 3 2 sdram containing 1,073,741,824 bits. it is internally configured as an octal - bank dram. the 1gb chip is organized as 32 mbit x 4 i/o x 8 , 16 mbit x 8 i/o x 8 bank or 8mbit x 16 i/o x 8 bank device. these synchronous devices achieve high speed double - data - rate transfer rates of up to 1600 mb/sec/pin for general appli cations. the chip is designed to comply w ith all key ddr 3 dram key features and a ll of the control and address inputs are synchronized with a pair of externally supplied differential clocks. inputs are latched at the cross point of differential clocks (ck rising and ?? falling). all i/os are synchronized with a single ended dqs or differential dqs pair in a source synchronous fash ion. these devices operate with a single 1. 5 v 0. 75 v power sup ply and are available in bga packages.
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 2 rev 1 . 2 0 1 / 200 9 pin configuration C 78 balls bga p ackage (x 4 ) < top view> see the balls through the package a b c d e f g x 4 1 vss vssq vdd vssq dq2 nc vddq vss ?? 2 nc dq0 dqs ??? nc ??? ??? 3 7 8 9 ba0 vdd nc vss vssq dq3 vss nc vss vdd nc dm dq1 nc ck ?? vddq h j k l vss vddq vrefdq a 3 a 5 vss vdd ?? ba2 a 0 a2 a1 a12/ ?? nc a10/ap vdd a4 ba1 verfca zq vddq vssq vssq vdd odt vss nc m n vdd a7 ????? a9 a13 vdd a6 a8 a11 nc vss vss nc nc vdd vss vss cke
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 3 rev 1 . 2 0 1 / 200 9 pin configuration C 78 balls bga package (x 8 ) < top view> see the balls through the package a b c d e f g x 8 1 vss vssq vdd vssq dq2 dq6 vddq vss ?? 2 nc dq0 dqs ??? dq4 ??? ??? 3 7 8 9 ba0 vdd nc vss vssq dq3 vss dq5 vss vdd nu/ ???? dm/tdqs dq1 dq7 ck ?? vddq h j k l vss vddq vrefdq a 3 a 5 vss vdd ?? ba2 a 0 a2 a1 a12/ ?? nc a10/ap vdd a4 ba1 verfca zq vddq vssq vssq vdd odt vss nc m n vdd a7 ????? a9 a13 vdd a6 a8 a11 nc vss vss nc nc vdd vss vss cke
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 4 rev 1 . 2 0 1 / 200 9 pin configuration C 96 balls bga pack age (x 16 ) < top view> see the balls through the package a b c d e f g x 16 1 vddq vssq dqu5 vdd dqu3 vddq vssq dql2 ???? 2 dqu7 vss dqu1 dmu dql0 dqsl ???? 3 7 8 9 vss vss vddq vddq dqu6 dqu2 vssq vssq dql3 vss dqu4 ???? dqsu dml dql1 vdd vddq h j k l vssq vddq vss vdd ?? nc dql6 dql4 ??? ??? ?? a10/ap ?? ck dql7 dqu0 zq vdd vss dql5 vssq vddq vdd cke vssq nc vssq m n vss ba0 a3 ba2 a0 vss vrefca ba1 nc a12 vdd vdd vddq vrefdq odt nc nc vssq p a 5 vss a2 a1 a4 r t vdd a7 ????? a9 nc vdd a6 a8 a11 nc vss vss vss
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 5 rev 1 . 2 0 1 / 200 9 input / output functional description symbol type function ck, ?? input clock: ck and ?? are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ?? . cke input clock enable: cke high activates, and cke low deactivates, internal c lock signals and device input buffers and output drivers. taking cke low provides precharge power - down and self - refresh operation (all banks idle), or active power - down (row active in any bank). cke is synchronous for power down entry and exit and for self - refresh entry. cke is asynchronous for self - refresh exit. after v ref has become stable during the power on and initialization sequence, it must be maintained for proper operation of the cke receiver. for proper self - refresh entry and exit, v ref must maint ain to this input. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ?? , odt and cke are disabled during power down. input buffers, excluding cke, are disabled during self - refresh. ?? input chip select: all comm and s are masked when ?? is registered high. ?? provides for external rank selection on systems with multiple memory ranks. ?? is considered part of the command code. ??? , ??? , ?? input command inputs: ??? , ??? and ?? (along with ?? ) define the command b eing entered. dm, ( dm u , dm l) input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. for x8 device, the funct ion of dm or t dqs / ? ??? is enabled by mode register a11 setting in mr1 ba0 - ba2 input bank address inputs: ba0, ba1, and ba2 define to which bank an active, read, write or precharge command is being applied. bank address also determines which mode register is to be accesse d during a mrs cycle. a0 C a13 input address inputs: provide the row address for activate commands and the column address for read/write commands to select one location out of the memory array in the respective bank. (a10/ap and a12/bc# have additional fu nction as below. the address inputs also provide the op - code during mode register set commands. a13 did not apply on x16 device . a12 / bc# input burst chop: a12/ ?? is sampled during read and write commands to determine if burst chop (on the fly) will be performed. (high - no burst chop; low - burst chopped). dq input/output data inputs/output: bi - directional data bus. dqu, dql dqs, ( ??? ) dqs l , ( ??? ? ), dqs u ,( ?? ? ? ) input/output data strobe: output with read data, input with write data. edge aligned with read data, centered with write data. for the x16, dqs l corresponds to the data on dq l 0 - dq l 7; dqs u corresponds to the data on dq u0 - dq u7 . the data strobes dqs, d qs l , dqs u are paire d with differential signals ??? , ???? , ???? , respectively, to provide differential pair signaling to the system during both reads and writes. ddr3 sdram supports differential data strobe only and does not support single - ended.
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 6 rev 1 . 2 0 1 / 200 9 symbol t ype function odt input on die termination: odt (registered high) enables termination resistance internal to the ddr3 sdram. when enabled, odt is applied to each dq, dqs, dqs# and dm/tdqs, nu/tdqs# (when tdqs is enabled via mode register a11=1 in mr1) sign al for x8 configurations. for x16 configuration odt is applied to each dq, dqsu, dqsu#, dqsl, dqsl#, dmu and dml signal. the odt pin will be ignored if mr1and mr2 are programmed to disable rtt. ????? ? input active low asynchronous reset: reset is active when reset# is low, and inactive when reset# is high. reset# must be high during normal operation. reset# is a cmos rail to rail signal with dc high and low at 80% and 20% of vdd, i.e. 1.20v for dc high and 0.30v nc no connect: no internal electrical connection is present. v ddq supply dq power supply: 1. 5 v 0. 075 v v dd supply power supply: 1. 5 v 0. 075 v v ssq supply dq ground v ss supply ground v refca supply reference voltage for ca v re fdq supply r e ference voltage for dq zq supply reference pin for zq calibration. note: input only pins (ba0 - ba2, a0 - a13, ??? , ??? , ?? , ?? , cke , odt, and ????? ) do not supply termination. ddr3 sdram addressing configuration nt5cb256m4an nt5cu128m8an nt5 cb64m16ap # of bank 8 8 8 bank address ba0 C ba2 ba0 C ba2 ba0 C ba2 auto precharge a10 / ap a10 / ap a10 / ap bl switch on the fly a12 / ?? ? a12 / ?? ? a12 / ?? ? row address a0 C a13 a0 C a13 a0 C a1 2 column address a0 C a9, a11 a0 C a9 a0 C a9 page si ze 1kb 1kb 2 kb note: page size is the number of data delivered from the array to the internal sense amplifiers when an active command is registered. page size is per bank, calculated as follows: page size = 2 colbits * org / 8 colbits = the number of c olumn address bits ort = the number of i/o (dq) bits
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 7 rev 1 . 2 0 1 / 200 9 ordering information green organization part number package speed clock (mbp / s) data rate (mb/s) cl - t rcd - t rp 256m x 4 nt5cb256m4an - ac 78 - ball w bga 0.8mmx0.8mm pitch 400 ddr3 - 800 5 - 5 - 5 nt5cb256 m4an - ad 400 ddr3 - 800 6 - 6 - 6 nt5cb256m4an - be 533 ddr3 - 1066 7 - 7 - 7 nt5cb256m4an - bf 533 ddr3 - 1066 8 - 8 - 8 nt5cb256m4an - cf 667 ddr3 - 1333 8 - 8 - 8 nt5cb256m4an - cg 667 ddr3 - 1333 9 - 9 - 9 nt5cb256m4an - dg 800 ddr3 - 1600 9 - 9 - 9 nt5cb256m4an - dh 800 ddr3 - 1600 10 - 10 - 10 128m x 8 nt5cb128m8an - ac 400 ddr3 - 800 5 - 5 - 5 nt5cb128m8an - ad 400 ddr3 - 800 6 - 6 - 6 nt5cb128m8an - be 533 ddr3 - 1066 7 - 7 - 7 nt5cb128m8an - bf 533 ddr3 - 1066 8 - 8 - 8 nt5cb128m8an - cf 667 ddr3 - 1333 8 - 8 - 8 nt5cb128m8an - cg 667 ddr3 - 1333 9 - 9 - 9 nt5cb 128m8an - dg 800 ddr3 - 1600 9 - 9 - 9 nt5cb128m8an - dh 800 ddr3 - 1600 10 - 10 - 10 64m x 16 nt5cb64m16ap - ac 96 - ball w bga 0.8mmx0.8mm pitch 400 ddr3 - 800 5 - 5 - 5 nt5cb64m16ap - ad 400 ddr3 - 800 6 - 6 - 6 nt5cb64m16ap - be 533 ddr3 - 1066 7 - 7 - 7 nt5cb64m16ap - bf 533 ddr3 - 1 066 8 - 8 - 8 nt5cb64m16ap - cf 667 ddr3 - 1333 8 - 8 - 8 nt5cb64m16ap - cg 667 ddr3 - 1333 9 - 9 - 9 nt5cb64m16ap - dg 800 ddr3 - 1600 9 - 9 - 9 nt5cb64m16ap - dh 800 ddr3 - 1600 10 - 10 - 10
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 8 rev 1 . 2 0 1 / 200 9 simplified state diagram p o w e r o n p o w e r a p p l i e d r e s e t p r o c e d u r e f r o m a n y s t a t e r e s e t i n i t i a l i z a t i o n z q c a l i b r a t i o n i d l e m r s , m p r , w r i t e l e v e l i z i n g s e l f r e f r e s h r e f r e s h i n g s r e s r x r e f a c t i v a t i n g a c t p r e c h a r g e p o w e r d o w n p d e p d x a c t i v e p o w e r d o w n b a n k a c t i v e w r i t i n g w r i t i n g p r e c h a r g i n g r e a d i n g w r i t e w r i t e a r e a d a w r i t e r e a d w r i t e a r e a d a w r i t e r e a d p r e , p r e a p r e , p r e a w r i t e a r e a d a p r e , p r e a p d x p d e r e a d i n g r e a d a u t o m a t i c s e q u e n c e c o m m a n d s e q u e n c e m r s z q c l z q c l z q c s abbreviation function abbreviation function abbreviation function act active read rd, rds4, rds8 ped enter power-down pre precharge read a rda, rdas4, rdas8 pdx exit power-down prea precharge all write wr, wrs4, wrs8 sre self-refresh entry mrs mode register set write a wra, wras4, wras8 srx self-refresh exit ref refresh reset# start reset procedure mpr multi-purpose register zqcl zq calibration long zqcs zq calibration short - -
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 9 rev 1 . 2 0 1 / 200 9 basic functionality the ddr3 sdram is a high - speed dynamic random access memory internally configured as an eight - bank dram. the ddr3 sdram uses a n 8n prefetch architecture to achieve high speed operation. the 8n prefetch architecture is combined with an i nterface designed to transfer two data words per clock cycle at the i/o pins. a single read or write operation for the ddr3 s dram consists of a single 8n - bit wide, four clock data transfer at the internal dram core and two corresponding n - bit wide, one - hal f clock cycle data transfers at the i/o pins. read and write operation to the ddr3 sdram are burst oriented, start at a selected location, and continue for a burst length of eight or a ?chopped? burst of four in a programmed sequence. operation begins with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the ba nk and row to be activated (ba0 - ba2 select the bank; a0 - a13 select the row). the address bit registered coinci dent with the read or write command are used to select the starting column location for the burst operation, determine if the auto precharge comman d is to be issued (via a10), and select bc4 or bc8 mode ?on the fly? (via a 12) if enabled in the mode register. prior to normal operation, the ddr3 sdram must be powered up and initialized in a predefined manner. the following sections provide detailed information covering device reset and initialization, register definition, com mand descriptions and device oper ation. dram initialization and reset power - up initialization sequence the following sequence is required for power up and initialization 1. apply power ( reset# is recommended to be maintained below 0.2 x vdd, all other in puts may be undefined). reset# needs to be maintained for minimum 200us with stable power. cke is pulled low anytime before reset# being de - asserted (min. time 10ns). the power voltage ramp time between 300mv to vddmin must be no greater than 200ms; and during the ramp, vdd>vddq and (vdd - vddq)<0.3 volts. - vdd and vddq are driven from a single power converter output, and - the voltage levels on all pins other than vdd, vddq, vss, vssq must be less than or equal to vddq and vdd on one side and must be lar ger than or equal to vssq and vss on the other side. in addition, vtt is limited to 0.95v max once power ramp is finished, and - vref tracks vddq/2. or - apply vdd without any slope reversal before or at the same time as vddq. - apply vddq without any slop e reversal before or at the same time as vtt & vref. - the voltage levels on all pins other than vdd, vddq, vss, vssq must be less than or equal to vddq and vdd on one side and must be larger than or equal to vssq and vss on the other side. 2. after reset# is de - asserted, wait for another 500us until cke become active. during this time, the dram will start inter nal state initialization; this will be done independently of external clocks.
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 10 rev 1 . 2 0 1 / 200 9 3. clock (ck, ck# ) need to be started and stabilized for at least 10n s or 5tck (which is larger) before cke goes active. since cke is a synchronous signal, the corresponding set up time to clock (tis) must be meet. also a nop or deselect command must be registered (with tis set up time to clock) before cke goes active. once the cke registered high after reset , cke needs to be continuously registered high until the initialization sequence is finished, including expi ration of tdllk and tzqinit. 4. the ddr3 dram will keep its on - die termination in high impedance state as l ong as reset# is asserted. further, the dram keeps its on - die termination in high impedance state after reset# deassertion until cke is registered high. the odt input signal may be in undefined state until tis before cke is registered high. when cke is reg istered high, the odt input signal may be statically held at either low or high. if rtt_nom is to be enabled in mr1, the odt input signal must be statically held low. in all cases, the odt input signal remains static until the power up initialization seque nce is finished, including the expiration of tdllk and tzqinit. 5. after cke being registered high, wait minimum of reset cke exit time, txpr, before issuing the first mrs command to load mode register. [txpr=max(txs, 5tck)] 6. issue mrs command to load mr 2 with all application settings. (to issue mrs command for mr2, provide low to ba0 and ba2, high to ba1) 7. issue mrs command to load mr3 with all application settings. (to issue mrs command for mr3, provide low to ba2, high to ba0 and ba1) 8. issu e mrs command to load mr1 with all application settings and dll enabled. (to issue dll enable command, pro vide low to a0, high to ba0 and low to ba1 and ba2) 9. issue mrs command to load mr0 with all application settings and dll reset. (to issue dll reset command, provide high to a8 and low to ba0 - ba2) 10. issue zqcl command to starting zq calibration. 11. wait for both tdllk and tzqinit completed. 12. the ddr3 sdram is now ready for normal operation.
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 11 rev 1 . 2 0 1 / 200 9 d dr3 reset and initialization sequence at power - on ramping d dr3 reset procedure at power stable condition the following sequence is required for reset at no power interruption initialization. 1. asserted reset below 0.2*vdd anytime when reset is needed (all other i nputs may be undefined). reset needs to be maintained for minimum 100ns. cke is pulled low before reset being de - asserted (min. time 10ns). 2. follow power - up initialization sequence step 2 to 11. 3. the reset sequence is now completed . ddr3 sdram is re ady for normal operation. c k c k t c k s r x r e s e t c k e t i s o d t c o m m a n d b a 0 - b a 2 t = 2 0 0 u s t = 5 0 0 u s t x p r t m r d t m r d t m r d t m o d t z q i n i t . d o n o t c a r e t i m e b r e a k 1 0 n s m r s m r s m r s m r s z q c l m r 2 m r 3 m r 1 m r 0 v d d , v d d q * f r o m t i m e p o i n t t d u n t i l t k . n o p o r d e s c o m m a n d s m u s t b e a p p l i e d b e t w e e n m r s a n d z q c a l c o m m n a d s . t e t k n o p * n o p * v a l i d v a l i d s t a t i c l o w i n c a s e r t t _ n o m i s e n a b l e d a t t i m e t g , o t h e r w i s e s t a t i c h i g h o r l o w t d t c t a t b t f t g t h t i t j t d l l k v a l i d v a l i d c k c k t c k s r x r e s e t c k e t i s o d t c o m m a n d b a 0 - b a 2 t = 1 0 0 n s t = 5 0 0 u s t x p r t m r d t m r d t m r d t m o d t z q i n i t . d o n o t c a r e t i m e b r e a k 1 0 n s m r s m r s m r s m r s z q c l m r 2 m r 3 m r 1 m r 0 v d d , v d d q * f r o m t i m e p o i n t t d u n t i l t k . n o p o r d e s c o m m a n d s m u s t b e a p p l i e d b e t w e e n m r s a n d z q c a l c o m m n a d s . t e t k n o p * n o p * v a l i d v a l i d s t a t i c l o w i n c a s e r t t _ n o m i s e n a b l e d a t t i m e t g , o t h e r w i s e s t a t i c h i g h o r l o w t d t c t a t b t f t g t h t i t j t d l l k v a l i d v a l i d
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 12 rev 1 . 2 0 1 / 200 9 register definition programming the mode registers for application flexibility, various functions, features, and modes are programmable in four mode registers, provided by the ddr3 sdram, as use r defined variables and they must be programmed via a mode register set (mrs) command. as the default values of the mode registers (mr#) are not defined, contents of mode registers must be fully initialized and/or re - initial ized, i.e. written, after power up and/or reset for proper operation. also the contents of the mode registers can be altered by re - executing the mrs command during normal operation. when programming the mode registers, even if the user chooses to modify only a sub - set of the mrs fields, all address fields within the accessed mode register must be redefined when the mrs command is issued. mrs command and dll reset do not affect array contents, which means these commands can be exe cuted any time after power - up without affecting the array contents the mode register set command cycle time, tmrd is required to complete the write operation to the mode register and is the mi nimum time required between two mrs commands shown as below. the mrs command to non - mrs comm and delay, tmod, is require for the dram to update the features except dll reset, and is the minimum time required from an mrs command to a non - mrs command excluding nop and des shown as the following figure. the mode register contents can be changed using the same command and timing requirements during normal operation as long as c k c k c k e d o n o t c a r e t i m e b r e a k m r s n o p n o p n o p n o p c m d v a l v a l a d d r t m r d m r s c k c k c k e m r s n o p n o p n o p n o p c m d a d d r t m o d n o n m r s v a l o l d s e t t i n g u p d a t i n g s e t t i n g n e w s e t t i n g v a l v a l
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 13 rev 1 . 2 0 1 / 200 9 the dram is in idle state, i.e. all banks are in the precharged state with trp satisfied, all data bursts are completed and c ke is high prior to writ ing into the mode register. the mode registers are divided into various fields depending on the function ality and/or modes. the mode register mr0 stores data for controlling various operating modes of ddr3 sdram. it controls burst length, read burst type, cas latency, test mode, dll reset, wr, and dll control for precharge power - down, which include various vendor specific options to make ddr3 sdram useful for various applications. the mode register is written by asserting low on cs#, ras#, cas#, we#, ba0, ba1, and ba2, while controlling the states of address pins according to the following figure. mr0 definition a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 1 0 a 1 1 a 1 2 a 1 3 b a 0 b a 1 b a 2 a d d r e s s f i l e d b l a 0 a 1 8 ( f i x e d ) 0 0 b c 4 o r 8 ( o n t h e f l y ) 1 0 b u r s t l e n g t h b u r s t t y p e a 3 n i b b l e s e q u e n t i a l 0 i n t e r l e a v e 1 b u r s t t y p e m r s m o d e b a 0 b a 1 m r 0 0 0 1 0 m r s m o d e 0 1 1 1 d l l c o n t r o l f o r p r e c h a r g e p d a 1 2 s l o w e x i t ( l o w p o w e r ) 0 f a s t e x i t ( n o r m a l ) 1 p r e c h a r g e p o w e r d o w n * * w r ( c y c l e s ) a 9 a 1 0 a 1 1 r e s e r v e d 0 0 0 5 1 0 0 w r i t e r e c o v e r y f o r a u t o p r e c h a r g e * * 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 d l l r e s e t a 8 n o 0 y e s 1 d l l r e s e t m o d e a 7 n o r m a l 0 t e s t 1 m o d e * b a 2 a n d a 1 3 a r e r e s e r v e d f o r f u t u r e u s e a n d m u s t b e s e t t o 0 w h e n p r o g r a m m i n g t h e m r . * * w r ( w r i t e r e c o v e r y f o r a u t o p r e c h a r g e ) m i n i n c l o c k c y c l e s i s c a l c u l a t e d b y d i v i d i n g t w r ( n s ) b y t c k ( n s ) a n d r o u n d i n g u p t o t h e n e x t i n t e g e r : w r m i n [ c y c l e s ] = r o u n d u p ( t w r / t c k ) . t h e v a l u e i n t h e m o d e r e g i s t e r m u s t b e p r o g r a m m e d t o b e e q u a l o r l a r g e r t h a n w r m i n . t h e p r o g r a m m e d w r v a l u e i s u s e d w i t h t r p t o d e t e r m i n e t d a l . c a s l a t e n c y a 2 a 4 a 5 0 0 0 5 0 c a s l a t e n c y 0 1 1 1 b c 4 ( f i x e d ) r e s e r v e d r e s e r v e d a 6 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0 6 7 8 9 1 0 r e s e r v e d 6 7 8 1 0 1 2 r e s e r v e d m r 1 m r 2 m r 3
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 14 rev 1 . 2 0 1 / 200 9 burst length, type, and order accesses within a given burst may be programmed to sequential or interleaved order. the burst type is selected via bit a3 as shown in the mr0 definition as above figure. the ordering of access within a burst is determined by the burst length, burst type, and the starting column address. the burst length is defined by bits a0 - a1. burst length options include fix bc4, fixed bl8, and on the fly which allow bc4 or bl8 to be selected coincident with the registration of a read or write command via a12 / ?? . burst type and burst order burst length read/ write starting column address (a2,a1,a0) burst type = sequential (decimal) a3 = 0 burst type = interleaved (decimal) a3 = 1 note 000 0,1,2,3,t,t,t,t 0,1,2,3,t,t,t,t 001 1,2,3,0,t,t,t,t 1,0,3,2,t,t,t,t 010 2,3,0,1,t,t,t,t 2,3,0,1,t,t,t,t 011 3,0,1,2,t,t,t,t 3,2,1,0,t,t,t,t 100 4,5,6,7,t,t,t,t 4,5,6,7,t,t,t,t 101 5,6,7,4,t,t,t,t 5,4,7,6,t,t,t,t 110 6,7,4,5,t,t,t,t 6,7,4,5,t,t,t,t 111 7,4,5,6,t,t,t,t 7,6,5,4,t,t,t,t 0,v,v 0,1,2,3,x,x,x,x 0,1,2,3,x,x,x,x 1,v,v 4,5,6,7,x,x,x,x 4,5,6,7,x,x,x,x 0 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 1 1,2,3,0,5,6,7,4 1,0,3,2,5,4,7,6 10 2,3,0,1,6,7,4,5 2,3,0,1,6,7,4,5 11 3,0,1,2,7,4,5,6 3,2,1,0,7,6,5,4 100 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 101 5,6,7,4,1,2,3,0 5,4,7,6,1,0,3,2 110 6,7,4,5,2,3,0,1 6,7,4,5,2,3,0,1 111 7,4,5,6,3,0,1,2 7,6,5,4,3,2,1,0 write v,v,v 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 2,4 note: 1. in case of burst length being fixed to 4 by mr0 setting, the internal write operation starts two clock cycles earlier than the bl8 mode. this means that the starting point for twr and twtr will be pulled in by two clocks. in case of burst length being selected on-th-fly via a12/ ?? , the internal write operation starts at the same point in time like a burst of 8 write operation. this means that during on-the-fly control, the starting point for twr and twtr will not be pulled in by two clocks. 2. 0~7 bit number is value of ca[2:0] that causes this bit to be the first read during a burst. 3. t: output driver for data and strobes are in high impedance. 4. v: a valid logic level (0 or 1), but respective buffer input ignores level on input pins. 5. x: do not care. write read 4 chop 1,2,3 1,2,4,5 read 2 8
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 15 rev 1 . 2 0 1 / 200 9 cas latency the cas latency is defined by mr0 (bit a9~a11) as shown in the mr0 definition figure. cas latency is the delay, in clock cycl es, between the internal read command and the availability of the first bit of output data. ddr3 sdram does not support any half clock latencies. the overall read latency (rl) is defined as additive latency (al) + cas latency (cl); rl = al + cl. test mode the normal operating mode is selected by mr0 (bit7=0) and all other bits set to the desired values shown in the mr0 definition figure. programming bit a7 to a ?1? places the ddr3 sdram into a test mode that is only used by the dram manufacturer and should not be used. no operations or functionality is guaranteed if a7=1. dll reset the dll reset bit is self - clearing, meaning it returns back to the value of ?0? after the dll reset function has been issued. once the dll is enabled, a subsequent dll reset should be applied. anytime the dll reset function is used, tdll k must be met before any functions that require the dll can be used. (i.e. read commands or odt synchronous operations) precharge pd dll mr0 (bit a12) is used to select the dll usage during precharge power - down mode. when mr0 (a12=0), or ?slow - exit?, the d ll is frozen after entering precharge power - down (for potential power savings) and upon exit requires txpdll to be met prior to the next valid command. when mr0 (a12=1), or ?fast - exit?, the dll is maintained after entering precharge power - down and upon exi ting power - down requires txp to be met prior to the next valid command. write recovery the programmed wr value mr0(bits a9, a10, and a11) is used for the auto precharge feature along with trp to determine tdal wr (write recovery for auto - precharge)min in c lock cycles is calculated by dividing twr(ns) by tck(ns) and rounding up to the next integer: wrmin[cycles] = roundup(twr[ns]/tck[ns]). the wr must be programmed to be equal or larger than twr(min).
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 16 rev 1 . 2 0 1 / 200 9 mode register mr1 the mode register mr1 stores the data for enabling or disabling the dll, output strength, rtt_nom impedance, additive latency, w rite leveling enable and qoff. the mode register 1 is written by asserting low on ?? , ??? , ??? , ?? high on ba0 and low on ba1 and ba2, while controlling the states of address pins according to the following figure. a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 1 0 a 1 1 a 1 2 a 1 3 b a 0 b a 1 b a 2 a d d r e s s f i l e d d l l e n a b l e a 0 e n a b l e 0 d i s a b l e 1 d l l o u t p u t d r i v e r i m p e d a n c e c o n t r o l m r b a 0 b a 1 m r 0 0 0 m r 1 1 0 m o d e r e g i s t e r 0 1 1 1 m r 3 m r 2 q o f f * * * b a 2 , a 5 , a 8 , a 1 0 , a n d a 1 3 a r e r e s e r v e d f o r f u t u r e u s e a n d m u s t b e s e t t o 0 w h e n p r o g r a m m i n g t h e m r . * * o u t p u t s d i s a b l e d C d q s , d q s s , d q s s . * * * i n w r i t e l e v e l i n g m o d e ( m r 1 [ b i t 7 ] = 1 ) w i t h m r 1 [ b i t 1 2 ] = 1 , a l l r t t _ n o m s e t t i n g s a r e a l l o w e d ; i n w r i t e l e v e l i n g m o d e ( m r 1 [ b i t 7 ] = 1 ) w i t h m r 1 [ b i t 1 2 ] = 0 , o n l y r t t _ n o m s e t t i n g o f r z q / 2 , r z q / 4 , a n d r z q / 6 a r e a l l o w e d . * * * * i f r t t _ n o m i s u s e d d u r i n g w r i t e s , o n l y t h e v a l u e s r z q / 2 , r z q / 4 , r z q / 6 a r e a l l o w e d . q o f f a 1 2 o u t p u t b u f f e r e n a b l e d 0 o u t p u t b u f f e r d i s a b l e d 1 a l a 3 a 4 0 ( a l d i s a b l e ) 0 0 c l - 1 1 0 a d d i t i v e l a t e n c y 0 1 1 1 r t t _ n o m a 2 a 6 a 9 o d t d i s a b l e 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 o d t v a l u e r z q / 4 r z q / 2 r z q / 6 r z q / 1 2 r z q / 8 r e s e r v e d r e s e r v e d * c l - 2 r e s e r v e d * * w r i t e l e v e l i z a t i o n w r i t e l e v e l i n g e n a b l e a 7 d i s a b l e d 0 e n a b l e d 1 t d q s t d q s e n a b l e a 1 1 d i s a b l e d 0 e n a b l e d 1 d . i . c . a 1 a 5 r e s e r v e d f o r r z q / 6 0 0 r z q / 7 1 0 0 1 1 1 r z q / t b d r z q / t b d * * * * * n o t e : r z q = 2 4 0 o h m s * * * * * * * *
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 17 rev 1 . 2 0 1 / 200 9 dll enable/disable the dll must be enabled for normal operation. dll enable is required duri ng power up initialization, and upon returning to nor mal operation after having the dll disabled. during normal operation (dll - on) with mr1 (a0=0), the dll is automatically dis abled when entering self - refresh operation and is automatically re - enable upon exit of self - refresh operation. any time the dll is enabled and subsequently reset, tdllk clock cycles must occur before a read or synchronous odt command can be issued to allow time for th e internal clock to be synchronized with the external clock. faili ng to wait for synchronization to occur may result in a violation of the tdqsck, taon, or taof parameters. during tdllk, cke must continuously be registered high. ddr3 sdram does not require dll for any write operation, expect when rtt_wr is enabled and th e dll is required for proper odt operation. for more detailed information on dll disable operation in dll - off mode. the direct odt feature is not supported during dll - off mode. the on - die termination resistors must be disabled by continu ously registering the odt pin low and/or by programming the rtt_nom bits mr1{a9,a6,a2} to {0,0,0} via a mode register set command during dll - off mode. the dynamic odt feature is not supported at dll - off mode. user must use mrs command to set rtt_wr, mr2{a10,a9}={0,0}, to di sable dynamic odt externally. output driver impedance control the output driver impedance of the ddr3 sdram device is selected by mr1(bit a1 and a5) as shown in mr1 definition figure. odt rtt values ddr3 sdram is capable of providing two different terminat ion values (rtt_nom and rtt_wr). the nominal termination value rtt_nom is programmable in mr1. a separate value (rtt_wr) may be programmable in mr2 to enable a unique rtt value when odt is enabled during writes. the rtt_wr value can be applied during write s even when rtt_nom is disabled. additive latency (al) additive latency (al) operation is supported to make command and data bus efficient for sustainable bandwidth in ddr3 sdram. in this operation, the ddr3 sdram allows a read or write command (either wi th or without auto - precharge) to be issued immediately after the active command. the command is held for the time of the additive latency (al) before it is issued inside the device . the read latency (rl) is controlled by the sum of the al and cas latency ( cl) register settings. write latency (wl) is controlled by the sum of the al and cas write latency (cwl) register settings. a summary of the al register options are shown as the following table. additive latency (al) settings a4 a3 al 0 0 0 (al disable) 0 1 cl - 1 1 0 cl - 2 1 1 reserved
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 1 8 rev 1 . 2 0 1 / 200 9 write leveling for better signal integrity, ddr3 memory module adopted fly by topology for the commands, addresses, control signals, and clo cks. the fly by topology has benefits from reducing number of stubs and their l ength but in other aspect, causes flight time skew between clock and strobe at every dram on dimm. it makes difficult for the controller to maintain tdqss, tdss, and tdsh specification . therefore, the controller should support ?write leveling? in ddr3 sdra m to compensate for skew. output disable the ddr3 sdram outputs maybe enable/disabled by mr1 (bit12) as shown in mr1 definition. when this feature is enabled (a12=1) all output pins (dqs, dqs , dqs# , etc.) are disconnected from the device removing any loadi ng of the output drivers. this feature may be useful when measuring modules power for example. for normal operation a12 should be set to ?0?. tdqs, ???? tdqs (termination data strobe) is a feature of x8 ddr3 sdram that provides additional termination resistance outputs that may be useful in some system configurations. tdqs is not supported in x4 and x16 configurations. when enabled via the mode regist er, the same termination resistance function is applied to be tdqs/ ???? pins that are applied to the dqs / ??? pins. in contrast to the rdqs function of ddr2 sdram, tdqs provides the termination resistance function only. the data strobe funct ion of rdqs is n ot provided by tdqs. the tdqs and dm functions share the same pin. when the tdqs function is enabled via the mode register, the dm function is not supported. when the tdqs function is disabled, the dm function is provided and the ???? pin is not used. the tdqs function is available in x8 ddr3 sdram only and must be disabled via the mode register a11=0 in mr1 for x4 and x16 configurations. tdqs, ???? mr1 (a11) dm / tdqs nu / tdqs 0 (tdqs disabled) dm hi - z 1 (tdqs enabled) tdqs tdqs note: 1. if tdqs is enabled, the dm function is disabled. 2. when not used, tdqs function can be disabled to save termination power. 3. tdqs function is only available for x8 dram and must be disabled for x4 and x16
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 19 rev 1 . 2 0 1 / 200 9 mode register mr2 the mode registe r mr2 stores the data for controlling refresh related features, rtt_wr impedance, and cas write latency. the mode register 2 is written by asserting low on ?? , ??? , ??? , ?? high on ba1 and low on ba0 and ba2, while controlling the states of address pins ac cording to the table below. a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 ba 0 ba 1 ba 2 address filed mrs mode ba 0 ba 1 mr 0 0 0 1 0 mrs mode 0 1 1 1 * * ba 2 , a 5 , a 8 , a 13 are reserved for future use and must be set to 0 when programming the mr . ** the rtt _ wr value can be applied during writes even when rtt _ nom is disabled . during write leveling , dynamic odt is not available . mr 1 mr 2 mr 3 cas write latency a 3 a 4 0 0 6 ( 2 . 5 ns > tck ( avg ) > = 1 . 875 ns ) 0 cas write latency 5 ( tck ( avg ) > = 2 . 5 ns ) a 5 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 7 ( 1 . 875 ns > tck ( avg ) > = 1 . 5 ns ) 8 ( 1 . 5 ns > tck ( avg ) > = 1 . 25 ns ) reserved reserved reserved reserved pasr a 0 a 1 0 0 half array ( 000 , 001 , 010 , 011 ) 0 pasr full array a 2 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 quarter array ( 000 , 001 ) 1 / 8 th array ( 000 ) 3 / 4 array ( 010 , 011 , 100 , 101 , 110 , 111 ) half array ( 100 , 101 , 110 , 111 ) quarter array ( 110 , 111 ) 1 / 8 th array ( 111 ) asr a 6 manual self refresh reference 0 asr enable 1 auto self refresh srt a 7 normal operating temperature range 0 extended operating temperature range 1 self - refresh temperature range a 9 a 10 dynamic odt off ( write does not affect rtt value ) 0 0 1 0 0 1 1 1 rzq / 4 reserved rtt _ wr ** rtt _ wr rzq / 2
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 20 rev 1 . 2 0 1 / 200 9 partial array self - refresh (pasr) if pasr (partial array self - refresh) is enabled, data located in areas of the array beyond the specified address range shown in mr2 will be lost if self - refresh is entered. data integrity will be maintained if trefi conditions are met and no self - refresh command is issued. cas write latency (cwl) the cas write latency is defined by mr2 (bits a3 - a5) shown in mr2. cas write latency is the delay, in clock cycles, betwe en the internal write command and the availability of the first bit of input data. ddr3 dram does not support any half clock laten cies. the overall write latency (wl) is defined as additive latency (al) + cas write latency (cwl); wl=al+cwl. auto self - re fresh (asr) and self - refresh temperature (srt) ddr3 sdram must support self - refresh operation at all supported temperatures. applications requiring self - refresh opera tion in the extended temperature range must use the asr function or program the srt bit a ppropriately. dynamic odt (rtt_wr) ddr3 sdram introduces a new feature dynamic odt. in certain application cases and to further enhance signal integrity on th e data bus, it is desirable that the termination strength of the ddr3 sdram can be changed with out issuing an mrs com mand. mr2 register locations a9 and a10 configure the dynamic odt settings.
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 21 rev 1 . 2 0 1 / 200 9 mode register mr3 the mode register mr3 controls multi purpose registers. the mode register 3 is written by asserting low on ?? , ??? , ??? , ?? high on ba1 and ba0, and low on ba2 while controlling the states of address pins according to the table below. multi - purpose register (mpr) the multi purpose register (mpr) function is used to read out a predef ined system timing calibration bit sequence. to enable the mpr, a mode register set (mrs) command must be issued to mr3 register with bit a2=1. prior to issuing the mrs com mand, all banks must be in the idle state (all banks precharged and trp met). once the mpr is enabled, any subsequent rd or rda commands will be redirected to the multi purpose register. when the mpr is enabled, only rd or rda commands are allowed until a subseq uent mrs command is issued with the mpr disabled (mr3 bit a2=0). power down m ode, self - refresh, and any other non - rd/rda command is not allowed during mpr enable mode. the reset function is supported during mpr enable mode. a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 ba 0 ba 1 ba 2 address filed mrs mode ba 0 ba 1 mr 0 0 0 1 0 mrs mode 0 1 1 1 note : ba 2 , a 3 - a 13 are reserved for future use and must be set to 0 when programming the mr . mr 1 mr 2 mr 3 mpr a 2 normal operation 0 dataflow from mpr 1 mpr mpr loc . a 0 a 1 0 0 rfu 0 mpr location predefined pattern 1 1 0 1 1 rfu thermal sensor readout
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 22 rev 1 . 2 0 1 / 200 9 ddr3 sdram command description and operation command truth table
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 23 rev 1 . 2 0 1 / 200 9 cke truth table no operation (nop) co mmand the no operation (nop) command is used to instruct the selected ddr3 sdram to perform a nop ( ?? low and ??? , ??? , and ?? high). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are n ot affected. deselect command the deselect function ( ?? high) prevents new commands from being execute d by the ddr3 sdram. the ddr3 sdram is effectively deselected. operations already in progress are not affected.
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 24 rev 1 . 2 0 1 / 200 9 dll - off mode ddr3 dll - off mode is entered by setting mr1 bit a0 to 1; this will disable the dll for subsequent operations until a0 bit set ba ck to 0. the mr1 a0 bit for dll control can be switched either during initialization or later. the dll - off mode operations listed below are an optional feature for ddr3. the maximum clock frequency for dll - off mode is specified by the parameter tckdll_of f. there is no minimum frequency limit besides the need to satisfy the refresh interval, trefi. due to latency counter and timing restrictions, only one value of cas latency (cl) in mr0 and cas write latency (cwl) in mr2 are supported. the dll - off mode is only required to support setting of both cl=6 and cwl=6. dll - off mode will affect the read data clock to data strobe relationship (tdqsck) but not the data strobe to data relationship (tdqsq, tqh). special attention is needed to line up read data to contro ller time domain. comparing with dll - on mode, where tdqsck starts from the rising clock edge (al+cl) cycles after the read command, the dll - off mode tdqsck starts (al+cl - 1) cycles after the read command. another difference is that tdqsck may not be small c ompared to tck (it might even be larger than tck) and the difference between tdqsckmin and tdqsckmax is significantly larger than in dll - on mode. the timing relations on dll - off mode read operation have shown at the following timing diagram (cl=6, bl=8) d ll - off mode read timing operation note: the tdqsck is used here for dqs, dqs , and dq to have a simplified diagram; the dll_off shift will affect both timings in the same way and the skew between all dq, dqs, and dqs# signals will still be tdqsq . ck ck t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 read cmd bank , col b address din b din b + 1 din b + 2 din b + 3 din b + 4 din b + 5 din b + 6 din b + 7 dqsdiff _ dll _ on dq _ dll _ on dqsdiff _ dll _ off dq _ dll _ off dqsdiff _ dll _ off dq _ dll _ off rl = al + cl = 6 ( cl = 6 , al = 0 ) rl ( dll _ off ) = al +( cl - 1 ) = 5 tdqsckdll _ diff _ min tdqsckdll _ diff _ max din b din b + 1 din b + 2 din b + 3 din b + 4 din b + 5 din b + 6 din b + 7 din b din b + 1 din b + 2 din b + 3 din b + 4 din b + 5 din b + 6 din b + 7
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 25 rev 1 . 2 0 1 / 200 9 dll on/off switching procedure ddr3 dll - off mode is entered by setting mr1 bit a0 to 1; this will disable the dll for subsequent operation until a0 bit set back to 0. dll on to dll off procedure to switch from dll on to dll off requires te f requency to be changed during self - refresh outlined in the following proce dure: 1. starting from idle state (all banks pre - charged, all timing fulfilled, and drams on - die termination resistors, rtt, must be in high impedance state before mrs to mr1 to disabl e the dll). 2. set mr1 bit a0 to 1 to disable the dll. 3. wait tmod. 4. enter self refresh mode; wait until (tcksre) satisfied. 5. change frequency, in guidance with input clock frequency change section. 6. wait until a stable clock is available for at least (tcksrx) at dram inputs. 7. starting with the self refresh exit command, cke must continuously be registered high until all tmod timings from any mrs command are satisfied. in addition, if any odt features were enabled in the mode registers when self refresh mode was entered, the odt signal must continuously be registered low until all tmod timings from any mrs command are sat isfied. if both odt features were disabled in the mode registers when self refresh mode was entered, odt signal can be registered low or high. 8. wait txs, and then set mode registers with appropriate values (especially an update of cl, cwl, and wr may be necessary. a zqcl command may also be issued after txs). 9. wait for tmod, and then dram is ready for next command. dll switch sequence from dll - on t o dll - off ck ck t 0 t 1 ta 0 ta 1 tb 0 tc 0 td 0 td 1 te 0 te 1 mrs 2 ) 1 ) cmd cke odt tmod tf 0 tcksre 4 ) tcksrx 5 ) txs tmod nop sre 3 ) nop srx 6 ) nop mrs 7 ) nop valid 8 ) tckesr valid 8 ) valid 8 ) time break do not care note: odt: static low in case rtt_nom and rtt_wr is enabled, otherwise static low or high 1) starting with idle state, rtt in hi-z state. 2) disable dll by setting mr1 bit a0 to 1. 3) enter sr. 4) change frequency. 5) clock must be stable at least tcksrx. 6) exit sr. 7) update mode registers with dll off parameters setting. 8) any valid command.
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 26 rev 1 . 2 0 1 / 200 9 dll off to dll on procedure to switch from dll off to dll on (with requires frequency change) during self - refresh: 1. starting from idle state (all banks pre - charged, all timings fulfilled and drams on - di e termination resistors (rtt) must be in high impedance state before self - refresh mode is entered). 2. enter self refresh mode, wait until tcksre satisfied. 3. change frequency, in guidance with input clock frequency change section. 4. wait until a stable is avai lable for at least (tcksrx) at dram inputs. 5. starting with the self refresh exit command, cke must continuously be registered high until tdllk timing from subse quent dll reset command is satisfied. in addition, if any odt features were enabled in the mode registers when self refresh mode was entered. the odt signal must continuously be registered low until tdllk timings from subsequent dll reset command is satisfied. if both odt features are disabled in the mode registers when self refresh mode was entered, odt signal can be registered low or high. 6. wait txs, then set mr1 bit a0 to 0 to enable the dll. 7. wait tmrd, then set mr0 bit a8 to 1 to start dll reset. 8. wait tmrd, then set mode registers with appropriate values (especially an update of cl, cwl, and wr may be necessary. after tmod satisfied from any proceeding mrs command, a zqcl command may also be issued during or after tdllk). 9. wait for tmod, then dram is ready for next command (remember to wait tdllk after dll reset before applying command requiring a locked dll!). in addition, wait also for tzqoper in case a zqcl command was issued. ck ck t 0 ta 0 ta 1 tb 0 tc 0 tc 1 td 0 te 0 tf 1 tg 0 1 ) cmd cke odt th 0 tcksre tcksrx 4 ) txs tmrd tdllk nop sre 2 ) srx 5 ) mrs 6 ) mrs 7 ) mrs 8 ) valid odtloff + 1 tck 3 ) tmrd valid tckesr time break do not care nop note: odt: static low in case rtt_nom and rtt_wr is enabled, otherwise static low or high 1) starting from idle state. 2) enter sr. 3) change frequency. 4) clock must be stable at least tcksrx. 5) exit sr. 6) set dll-on by mr1 a0="0" 7) start dll reset 8) any valid command
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 27 rev 1 . 2 0 1 / 200 9 input clock frequency change once the ddr3 sdram is initialized, the ddr3 sdram requires the clock to be stable during almost all states o f normal operation. this means once the clock frequency has been set and is to be in the stable state, the clock period is not allowed to devia te except for what is allowed for by the clock jitter and ssc (spread spectrum clocking) specification. the inp ut clock frequency can be changed from one stable clock rate to another stable clock rate under two conditions: (1) self - refresh mode and (2) precharge power - down mode. outside of these two modes, it is illegal to change the clock frequency. for the first condition, once the ddr3 sdram has been successfully placed in to self - refresh mode and tcksre has been satisfied, the state of the clock becomes a don?t care. once a don?t care, changing the clock frequency is permissible, provided the new clock frequency is stable prior to tcksrx. when entering and exiting self - refresh mode of the sole purpose of chang ing the clock frequency. the ddr3 sdram input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for th e particular speed grade. the second condition is when the ddr3 sdram is in precharge power - down mode (either fast exit mode or slow exit mode). if the rtt_nom feature was enabled in the mode register prior to entering precharge power down mode, the odt s ignal must continuously be registered low ensuring rtt is in an off state. if the rtt_nom feature was disabled in the mode register prior to engering precharge power down mode, rtt will remain in the off state. the odt signal can be registered either low o r high in this case. a minimum of tcksre must occur after cke goes low before the clock frequency may change. the ddr3 sdram input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular spe ed grade. during the input clock frequency change, odt and cke must be held at stable low levels. once the input clock frequency is cha nged, stable new clocks must be provided to the dram tcksrx before precharge power down may be exited; after precharge po wer down is exited and txp has expired, the dll must be reset via mrs. depending on the new clock frequency additional mrs commands may need to be issued to appropriately set the wr, cl, and cwl with cke continuously registered high. during dll re - lock per iod, odt must remain low and cke must remain high. after the dll lock time, the dram is ready to operate with new clock frequency.
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 28 rev 1 . 2 0 1 / 200 9 change frequency during precharge power - down write leveling for better signal integrity, ddr3 memory adopted fly by topology for the commands, addresses, control signals, and clocks. the fly by topology has benefits from reducing number of stubs and their length but in other aspect, causes flight time skew between clo ck and strobe at every dram on dimm. it makes it difficult for the controller to maintain tdqss, tdss, and tdsh specification. therefore, the controller should support write leveling in ddr3 sdram to compensate the skew. the memory controller can use the write leveling feature and feedback from the d dr3 sdram to adjust the dqs - ??? to ck - ?? relationship. the memory controller involved in the leveling must have adjustable delay setting on dqs - ??? to align the rising edge of dqs - ??? with that of the clock at the dram pin. dram asynchronously feed s back ck - ?? , sampled with the rising edge of dqs - ??? , through the dq bus. the controller repeatedly delays dqs - ??? until a transition from 0 to 1 is detected. the dqs - ??? delay established though this exercise would ensure tdqss specification. be sides tdqss, tdss, and tdsh specification also needs to be fulfilled. one way to achieve this is to combine the actual tdqss in the application with an appropriate duty cycle and jitter on the dqs - ??? signals. depending on the actual tdqss in the applicat ion, the actual val ues for tdqsl and tdqsh may have to be better than the absolute limits provided in ac timing parameters section in order to satisfy tdss and tdsh specification. a concep tual timing of this scheme is show as below figure. 0 or 1 0 0 diff _ ck diff _ dqs source diff _ ck diff _ dqs destination dq dq push dqs to capture 0 - 1 transition 0 or 1 1 1 ck ck t 0 t 1 t 2 ta 0 tb 0 tc 0 tc 1 td 0 td 1 te 0 cke command dqs , dqs tch tcl tck te 1 tih tis tih tis tcksre tcke tcksrx tchb tclb tckb nop nop nop nop nop mrs nop valid dll reset valid tih tis address odt dq dm high - z high - z taofpd / taof tcpded txp tdllk previous clock frequency new clock frequency frequency change enter precharge power - down mode exit precharge power - down mode
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 29 rev 1 . 2 0 1 / 200 9 dqs/ ??? driven by the controller during leveling mode must be determined by the dram based on ranks populated. similarly, the dq bus driven by the dram must also be terminated at the controller. one or more data bits should carry the leveling feedback to the c ontroller across the dram configurations x4, x8, and x16. on a x16 device, both byte lanes should be leveled independently. therefore, a separate feedback mechanism should be able for each byt e lane. the upper data bits should provide the feedback of the u pper diff_dqs (diff_udqs) to clock relationship whereas the lower data bits would indicate the lower diff_dqs (diff_ldqs) to clock relationship. dram setting for write leveling and dram termination unction in that mode dram enters into write leveling mode if a7 in mr1 set high and after finishing leveling, dram exits from write leveling mode if a7 in mr1 set low. note that in write leveling mode, only dqs/ ??? terminations are activated and deactivated via odt pin not like normal operation. mr setting i nvolved in the leveling procedure function mr1 enable disable write leveling enable a7 1 0 output buffer mode (qoff) a12 0 1 dram termination function in the leveling mode odt pin at dram dqs/dqs termination dqs termination de - asserted off off assert ed on off note: in write leveling mode with its output buffer disabled (mr1[bit7]=1 with mr1[bit12]=1) all rtt_nom settings are allowed ; in write leveling mode with its output buffer enabled (mr1[bit7]=1 with mr1[bit12]=0) only rtt_nom settings of rzq/2, rzq/4, and rzq/6 are allowed. procedure description memory controller initiates leveling mode of all drams by setting bit 7 of mr1 to 1. with entering write leveling mode, the d q pins are in undefined driving mode. during write leveling mode, only nop or d eselect commands are allowed. as well as an mrs command to exit write leveling mode. since the controller levels one rank at a time, the output of other rank must be dis abled by setting mr1 bit a12 to 1. controller may assert odt after tmod, time at which dram is ready to accept the odt sig nal. controller may drive dqs low and ??? high after a delay of twldqsen, at which time dram has applied on - die termination on these signals. after tdqsl and twlmrd co ntroller provides a single dqs, ??? edge which is us ed by the dram to sample ck C ?? driven from controller. twlmrd(max) timing is controller dependent. dram samples ck - ?? ? status with rising edge of dqs and provides feedback on all the dq bits asynchronously after twlo timing. there is a dq output uncerta inty of twloe defined to allow mismatch on dq bits; there are no read strobes (dqs/dqs) needed for these dqs. controller samples incoming dq and decides to increment or decrement dqs C ??? delay setting and launches the next dqs/ ??? pulse after some time, which is controller dependent. once a 0 to 1 transition is detected, the con troller locks dqs C ??? delay setting and write leveling is achieved for the device. the following figure describes the timing dia gram and parameters for the overall write leveli ng procedure.
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 30 rev 1 . 2 0 1 / 200 9 timing details of write leveling sequence [dqs - ??? ?? ?? write leveling mode exit the following sequence describes how write leveling mode should be exited: 1. afte r the last rising strobe edge (see ~t0), stop driving the strobe signals (see ~tc0). note: from now on, dq pins are in undefined d riving mode, and will remain undefined, until tmod after the respective mr command (te1). 2. drive odt pin low (tis must be sati sfied) and keep it low (see tb0). 3. after the rtt is switched off, disable write level mode via mrs command (see tc2). 4. af ter tmod is satisfied (te1), any valid command may be registered. (mr commands may be issued after tmrd (td1). timing detail of write l eveling exit nop nop nop nop nop nop nop nop nop ck ck cmd odt di ff _ dqs prime dq late re ma ini ng dqs tmod twlmr d twlo twls t wlh twloe twls t wlh t wlo nop m rs tdqsh tdqsl tdqsh t dqsl t 1 t 2 time break do not care one pri me dq : earl y re ma ini ng dqs twlo t wlo undefined driving mode twloe twlo t wlo all dqs are prime : late re ma ini ng dqs earl y re ma ini ng dqs twlmrd twlo t wlo t wloe twldqsen nop note: 1. dram has the option to drive leveling feedback on a prime dq or all dqs. if feedback is driven only on one dq, the remaining dqs must be driven low as shown in above figure, and maintained at this state through out the leveling procedure. 2. mrs: load mr1 to enter write leveling mode 3. nop: nop or deselect 4. diff_dqs is the differential data strobe (dqs, ??? ). timing reference points are the zero crossings. dqs is shown with solid line, ??? is shown with dotted line. 6. dqs/ ??? needs to fulfill minimum pulse width requirements tdqsh(min) and tdqsl(min) as defined for regular writes; the max pulse width is system dependent. ck ck t 0 t 1 ta 0 tc 0 tc 1 tc 2 td 1 te 1 cmd ba tis tmod tmrd odt rtt _ dqs _ dqs dqs _ dqs result = 1 twlo dq rtt _ nom td 0 te 0 t 2 tb 0 taofmin taofmax transitioning time break do not care undefined driving mode nop nop nop nop nop nop nop mrs nop valid nop valid mr 1 valid valid todtloff
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 31 rev 1 . 2 0 1 / 200 9 extended temperature usage a. auto self - refresh supported b. extended temperature range supported c. double refresh required for operation in the extended temperature range . mode register description field bits description asr mr2(a6) auto s elf - refresh (asr) when enabled, ddr3 sdram automatically provides self - refresh power management functions for all supported operating temperature values. if not enabled, the srt bit must be programmed to indicate toper during subsequent self - refresh operat ion. 0 = manual sr reference (srt) 1 = asr enable srt mr2(a7) self - refresh temperature (srt) range if asr = 0, the srt bit must be programmed to indicate toper during subsequent self - refresh operation. if asr = 1, srt bit must be set to 0. 0 = normal oper ating temperature range 1 = extended operating temperature range auto self - refresh mode - asr mode ddr3 sdram provides an auto - refresh mode (asr) for application ease. asr mode is enabled by setting mr2 bit a6=1 and mr2 bit a7=0. the dram will manage self - refresh entry in either the normal or extended temperature ranges. in this mode, the dram will also manage self - refresh power consumption when the dram operating temperature changes, lower at low temperatures and higher at high temperatures. if the asr op tion is not supported by dram, mr2 bit a6 must set to 0. if the asr option is not enabled (mr2 bit a6=0), the srt bit (mr2 bit a7) must be manually programmed with the operating temperature range required during self - refresh operation. support of the asr o ption does not automatically imply support of the extended temperature range. self - refresh temperature range - srt srt applies to devices supporting extended temperature range only. if asr=0, the self - refresh temperature (srt) range bit must be programmed to guarantee proper self - refresh operation. if srt=0, then the dram will set an appropriate refresh rate for self - refresh operation in the normal temperature range. if srt=1, then the dram will set an appropriate, potentially different, refresh rate to al low self - refresh operation in either the normal or extended temperature ranges. the value of the srt bit can effect self - refresh power consumption, please refer to idd table for details. self - refresh mode summary mr2 a[6] mr2 a[7] self - refresh operation allowed operating temperature range for self - refresh mode 0 0 self - refresh rate appropriate for the normal temperature range normal (0 ~ 85c) 0 1 self - refresh appropriate for either the normal or extended temperature ranges. the dram must support extende d temperature range. the value of the srt bit can effect self - refresh power consumption, please refer to the idd table for details. normal and extended (0 ~ 95c) 1 0 asr enabled (for devices supporting asr and normal temperature range). self - refresh power consumption is temperature dependent. normal (0 ~ 85c) 1 0 asr enabled (for devices supporting asr and extended temperature range). self - refresh power consumption is temperature dependent. normal and extended (0 ~ 95c) 1 1 illegal
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 32 rev 1 . 2 0 1 / 200 9 mpr mr3 register definition mr3 a[2] mr3 a[1:0] function 0 don't care (0 or 1) normal operation, no mpr transaction. all subsequent reads will come from dram array. all subsequent writes will go to dram array. 1 see the following table enable mpr mode , subsequent rd/rda commands defined by mr3 a[1:0]. mpr functional description one bit wide logical interface via all dq pins during read operation. register read on x4: dq [0] drives information from mpr. dq [3:1] either drive the same information as dq [0], or they drive 0. register read on x8: dq [0] drives information from mpr. dq [7:1] either drive the same information as dq [0], or they drive 0. register read on x16: dql [0] and dqu [0] drive information from mpr. dql [7:1] and dqu [7:1] either drive the same information as dql[0], or they drive 0. addressing during for multi purpose register reads for all mpr agents: ba [2:0]: don?t care. a [1:0]: a [1:0] must be equal to 00. data read burst order in nibble is fixed. a[2]: for bl=8, a[2] must be eq ual to 0, burst order is fixed to [0,1,2,3,4,5,6,7]; for burst chop 4 cases, the burst order is switched on nibble base, a[2]=0, burst order: 0,1,2,3, a[2]=1, burst order: 4,5,6,7. *) a [9:3]: don?t care. a10/ap: don?t care. a12/bc: selects burst chop mode on - the - fly, if enabled within mr0 a11, a13: don?t care. regular interface functionality during register reads: support two burst ordering which are switched with a2 and a[1:0]=00. support of read burst chop (mrs and on - the - fly via a12/bc). all other addre ss bits (remaining column addresses bits including a10, all bank address bits) will be ignored by the ddr3 sdram. regular read latencies and ac timings apply. dll must be locked prior to mpr reads. note *): burst order bit 0 is assigned to lsb and burst or der bit 7 is assigned to msb of the selected mpr agent.
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 33 rev 1 . 2 0 1 / 200 9 mpr register address definition the following table provide an overview of the available data location, how they are addressed by mr3 a[1:0] during a mrs to mr3, and how their individual bits are map ped into the burst order bits during a multi purpose register read. mpr mr3 register definition mr3 a[2] mr3 a[1:0] function burst length read address a[2:0] burst order and data pattern 1 00 read predefined pattern for system calibration bl8 000 burst o rder 0,1,2,3,4,5,6,7 pre - defined data pattern [0,1,0,1,0,1,0,1] bc4 000 burst order 0,1,2,3 pre - defined data pattern [0,1,0,1] bc4 100 burst order 4,5,6,7 pre - defined data pattern [0,1,0,1] 1 01 rfu bl8 000 burst order 0,1,2,3,4,5,6,7 bc4 000 burst order 0,1,2,3 bc4 100 burst order 4,5,6,7 1 10 rfu bl8 000 burst order 0,1,2,3,4,5,6,7 bc4 000 burst order 0,1,2,3 bc4 100 burst order 4,5,6,7 1 11 rfu bl8 000 burst order 0,1,2,3,4,5,6,7 bc4 000 burst order 0,1,2,3 bc4 100 burs t order 4,5,6,7 note: burst order bit 0 is assigned to lsb and the burst order bit 7 is assigned to msb of the selected mpr agent. active command the active command is used to open (or activate) a row in a particular bank for subsequent access. the value on the ba0 - ba2 inputs selects the bank, and the address es provided on inputs a0 - a13 selects the row. these rows remain active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a diff er ent row in the same bank. precharge command the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row activation a specified time (trp) after the precha rge command is issued, except in the case of concurrent auto precharge, where a read or write command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. on ce a bank has been pre charged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a pre charge command is allowed if there is no open row in that bank (idle bank) or if the previously open row is a lready in the process of precharging. however, the precharge period will be determined by the last precharge command issued to the bank.
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 34 rev 1 . 2 0 1 / 200 9 read operation read burst operation during a read or write command ddr3 will support bc4 and bl8 on the fly using add ress a12 during the read or write (auto precharge can be enabled or disabled). a12=0, bc4 (bc4 = burst chop, tccd=4) a12=1, bl8 a12 will be used only for burst length control, not a column address. read burst operation rl=5 (al=0, cl=5, bl=8) read burst operation rl = 9 (al=4, cl=5, bl=8) read timing definitions read timing is shown in the following figure and is applied when the dll is enabled and locked. rising data strobe edge parameters: tdqsck min/max describes the allowed range for a rising data s trobe edge relative to ck, ck. tdqsck is the actual position of a rising strobe edge relative to ck, ck. tqsh describes the dqs, ??? differential output high time. tdqsq describes the latest valid transition of the associated dq pins. tqh describes the ea rliest invalide transition of the associated dq pins. fal ling data strobe edge parameters: tqsl describes the dqs, ??? differential output low time. tdqsq describes the latest valid transition of the associated dq pins. tqh describes the earliest invalid transition of the associated dq pins. ck ck t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 145 cl = 5 dqs , dqs t 2 t 4 t 8 t 10 read nop cmd nop nop nop nop nop nop nop nop nop nop bank col n address dout n dout n + 1 dout n + 2 dout n + 3 dout n + 4 dout n + 5 dout n + 6 dout n + 7 dq rl = al + cl trpre trpst ck ck t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 145 cl = 5 dqs , dqs t 2 t 4 t 8 t 10 read nop cmd nop nop nop nop nop nop nop nop nop nop bank col n address dout n dout n + 1 dout n + 2 dout n + 3 dout n + 4 dout n + 5 dq rl = al + cl trpre al = 4
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 35 rev 1 . 2 0 1 / 200 9 read timing definition read timing; clock to data strobe relationship clock to data strobe relationship is shown in the following figure and is applied when the dll is enabled and locked. rising data str obe edge parameters: tdqsck min/max describes the allowed range for a rising data strobe edge relative to ck and ?? . tdqsck is the actual position of a rising strobe edge relative to ck and ?? . tqsh describes the data strobe high pulse width. falling data strobe edge parameters: tdsl describes the data strobe low pulse width. clock to data strobe relationship rising strobe region tdqsk , min tdqsk , max tdqsk ck ck dqs dqs tdqsk rising strobe region tqsh tqsl tqh tqh tdqsq tdqsq associated dq pins ck ck rl measured to this point dqs , dqs early strobe dqs , dqs late strobe tlz ( dqs ) min tlz ( dqs ) max trpre trpre tdqsckmin tdqsckmax tqsh tqsl trpst trpst thz ( dqs ) min thz ( dqs ) max
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 36 rev 1 . 2 0 1 / 200 9 read timing; data strobe to data relationship the data strobe to data relationship is shown in the following figure and is applied when the dll and enabled and locked. rising data strobe edge parameters: tdqsq describes the latest valid transition of the associated dq pins. tqh describes the earliest invalid transition of the associated dq pins. falling data strobe edge parameters: tdqsq describes the latest valid transition of the associated dq pins. tqh describes the earliest invalid transition of t he associated dq pins. data strobe to data relationship dout n + 6 dout n + 7 trpst ck ck t 0 t 1 t 3 t 5 t 6 t 7 t 9 dqs , dqs t 2 t 4 t 8 read nop cmd nop nop nop nop nop nop nop nop bank col n address dout n + 1 dout n + 2 dout n + 3 dout n + 4 dout n + 5 dq ( last data valid ) rl = al + cl trpre dout n + 6 dout n + 7 dout n dout n + 1 dout n + 2 dout n + 3 dout n + 4 dout n + 5 tlz ( dq ) min valid data thz ( dq ) min tdqsqmax valid data tqh tqh dout n tdqsqmin dq ( first data no longer valid ) all dq collectively
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 37 rev 1 . 2 0 1 / 200 9 read to read (cl=5, al=0) t 1 1 t 1 0 n o p n o p d o u t n + 6 d o u t n + 7 t r p s t c k c k t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 n o p c m d n o p n o p r e a d n o p n o p n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 t c c d t r p r e d o u t n t 1 2 n o p t 1 3 n o p r l = 5 b a n k c o l b r e a d d o u t b + 6 d o u t b + 7 d o u t b + 1 d o u t b + 2 d o u t b + 3 d o u t b + 4 d o u t b + 5 d o u t b r l = 5 d q s , d q s d q r e a d ( b l 8 ) t o r e a d ( b l 8 ) n o p n o p t r p s t n o p c m d n o p n o p r e a d n o p n o p n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 t c c d t r p r e d o u t n n o p n o p r l = 5 b a n k c o l b r e a d d o u t b + 1 d o u t b + 2 d o u t b + 3 d o u t b r l = 5 d q s , d q s d q r e a d ( b l 4 ) t o r e a d ( b l 4 ) t r p r e t r p s t r e a d b a n k c o l n r e a d b a n k c o l n
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 38 rev 1 . 2 0 1 / 200 9 read to write (cl=5, al=0; cwl=5, al=0) t 1 1 t 1 0 n o p d o u t n + 6 d o u t n + 7 t w p s t c k c k t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 n o p c m d n o p n o p w r i t e a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 r e a d t o w r i t e c o m m a n d d e l a y = r l + t c c d + 2 t c k - w l t r p r e d o u t n t 1 2 n o p t 1 3 n o p r l = 5 b a n k c o l b d o u t b + 7 d o u t b + 1 d o u t b + 2 d o u t b + 3 d o u t b + 4 d o u t b + 5 w l = 5 d q s , d q s d q r e a d ( b l 8 ) t o w r i t e ( b l 8 ) n o p t w p s t n o p c m d n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 r e a d t o w r i t e c o m m a n d d e l a y = r l + t c c d / 2 + 2 t c k - w l t r p r e d o u t n n o p n o p r l = 5 r e a d d o u t b + 1 d o u t b + 2 d o u t b + 3 w l = 5 d q s , d q s r e a d ( b l 4 ) t o w r i t e ( b l 4 ) t w p r e t r p s t t 1 4 t 1 5 n o p n o p t w r p r e t r p s t b a n k c o l n r e a d n o p n o p n o p n o p n o p n o p d q n o p n o p t b l = 4 c l o c k s t w r t w t r r e a d b a n k c o l n w r i t e b a n k c o l b n o p d o u t b n o p n o p n o p n o p d o u t b d o u t b + 6
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 39 rev 1 . 2 0 1 / 200 9 read to read (cl=5, al=0) t 1 1 t 1 0 n o p n o p d o u t n + 6 d o u t n + 7 t r p s t c k c k t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 n o p c m d n o p n o p n o p n o p n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 t c c d t r p r e d o u t n t 1 2 n o p t 1 3 n o p r l = 5 r e a d d o u t b + 1 d o u t b + 2 d o u t b + 3 d o u t b r l = 5 d q s , d q s d q r e a d ( b l 8 ) t o r e a d ( b c 4 ) n o p n o p t r p s t n o p c m d n o p n o p n o p n o p n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 t c c d t r p r e d o u t n n o p n o p r l = 5 r e a d r l = 5 d q s , d q s r e a d ( b c 4 ) t o r e a d ( b l 8 ) t r p r e t r p s t d q r e a d b a n k c o l n r e a d b a n k c o l n r e a d b a n k c o l b r e a d b a n k c o l b d o u t b + 6 d o u t b + 7 d o u t b + 1 d o u t b + 2 d o u t b + 3 d o u t b + 4 d o u t b + 5 d o u t b
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 40 rev 1 . 2 0 1 / 200 9 read to write (cl=5, al=0; cwl=5, al=0) t 1 1 t 1 0 n o p n o p d o u t n + 6 d o u t n + 7 t r p s t c k c k t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 n o p c m d n o p n o p w r i t e a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 t r p r e d o u t n t 1 2 n o p t 1 3 n o p r l = 5 r e a d d o u t b + 1 d o u t b + 2 d o u t b + 3 w l = 5 d q s , d q s d q n o p n o p t w p s t n o p c m d n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 r e a d t o w r i t e c o m m a n d d e l a y = r l + t c c d / 2 + 2 t c k - w l t r p r e d o u t n n o p n o p r l = 5 r e a d w l = 5 d q s , d q s r e a d ( b l 4 ) t o w r i t e ( b l 8 ) t w p r e t r p s t d q r e a d b a n k c o l n r e a d b a n k c o l n n o p b a n k c o l b w r i t e b a n k c o l b d o u t b + 6 d o u t b + 7 d o u t b + 1 d o u t b + 2 d o u t b + 3 d o u t b + 4 d o u t b + 5 d o u t b n o p n o p n o p n o p r e a d ( b l 8 ) t o w r i t e ( b c 4 ) n o p n o p n o p n o p t w p s t t w p r e d o u t b r e a d t o w r i t e c o m m a n d d e l a y = r l + t c c d + 2 t c k - w l
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 41 rev 1 . 2 0 1 / 200 9 write operation during a read or write command, ddr3 will support bc4 and bl8 on the fly using address a12 during the read or write (auto precharge can be enabled or disabled). a12=0, bc4 (bc4 = burst chop, tccd=4) a12=1, bl8 a12 is used only for burst length control, not as a column address. write timing violations motivation generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to make sure the dram works properly. however, it is desirable for certain minor violations that the dr am is guaranteed not to hang up and errors be limited to that particular operation. for the following, it will be assumed that there are no timing violations w.r.t. to the write command itself (including odt, etc.) and that it does satisfy all timing req uirements not mentioned below. data setup and hold violations should the strobe timing requirements (tds, tdh) be violated, for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with t he offending write command. subsequent reads from that location might result in unpredictable read data, however, the dram will work properly otherwise. strobe to strobe and strobe to clock violations should the strobe timing requirements (tdqsh, tdqsl, t wpre, twpst) or the strobe to clock timing requirements (tdss, tdsh, tdqss) be violated, for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with the offending write command. subseque nt reads from that location might result in unpredict able read data, however the dram will work properly otherwise. write timing parameters this drawing is for example only to enumerate the strobe edges that belong to a write burst. no actual timing vi olations are shown here. for a valid burst all timing parameters for each edge of a burst need to be satisfied (not only for one edge - as shown).
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 42 rev 1 . 2 0 1 / 200 9 write timing definition note: 1. bl=8, wl=5 (al=0, cwl=5). 2. din n = data in from column n. 3. nop comman ds are shown for ease of illustration; other command may be valid at these times. 4. bl8 setting activated by either mr0 [a1:0=00] or mr0 [a1:0=01] and a12 = 1 during write command at t0. 4. tdqss must be met at each rising clock edge. tn ck ck t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 nop cmd nop nop address dq nop w l = a l + c w l nop nop din n + 6 din n + 7 din n + 1 din n + 2 din n + 3 din n + 4 din n + 5 din n tdqss tdsh tdqsl tdss twpst ( min ) tdqsl ( min ) tdss tdss tdss tdss dq tdsh tdqsh tdqsl tdss tdqsh twpre ( min ) tdss tdsh tdqsh tdsh tdsh tdss tdss tdss dq din n + 6 din n + 7 din n + 1 din n + 2 din n + 3 din n + 4 din n + 5 din n tdsh tdqsh tdqsh tdsh tdqsh tdsh tdsh nop tdqsh twpre ( min ) write bank col n twpre ( min ) tdqsh nop tdss tdqsl tdss tdss nop tdsh tdsh din n + 6 din n + 7 din n + 1 din n + 2 din n + 3 din n + 4 din n + 5 din n tdqsh tdsh nop tdss tdss tdqsl ( min ) twpst ( min ) tdqsl ( min ) twpst ( min ) tdqss dqs , dqs ( tdqss min ) dqs , dqs ( tdqss nominal ) dqs , dqs ( tdqss max )
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 43 rev 1 . 2 0 1 / 200 9 write to write (wl= 5; cwl=5, al=0) t 1 1 t 1 0 n o p d o u t n + 7 c k c k t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 n o p c m d n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 5 t c c d t w p r e t 1 2 n o p t 1 3 n o p w l = 5 d o u t b + 6 d o u t b + 7 d o u t b + 1 d o u t b + 2 d o u t b + 3 d o u t b + 5 w l = 5 d q s , d q s d q w r i t e ( b l 8 ) t o w r i t e ( b l 8 ) n o p t w p s t n o p c m d n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 t c c d t r p r e n o p n o p w l = 5 r e a d d o u t b + 1 d o u t b + 2 d o u t b + 3 w l = 5 d q s , d q s w r i t e ( b c 4 ) t o w r i t e ( b c 4 ) t w p r e t w p s t t w p s t b a n k c o l n w r i t e n o p n o p n o p n o p n o p w r i t e d q w r i t e b a n k c o l n w r i t e b a n k c o l b n o p b a n k c o l b d o u t n n o p n o p n o p n o p d o u t n + 4 d o u t n + 6 d o u t b d o u t b + 4 t b l = 4 t w r t w t r t b l = 4 t w r t w t r d o u t n d o u t b
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 44 rev 1 . 2 0 1 / 200 9 write to read (rl=5, cl=5, al=0; wl=5, cwl=5, al=0; bl=4) t 1 1 t 1 0 n o p d o u t n + 7 c k c k t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 n o p c m d n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 5 t w p r e t 1 2 n o p t 1 3 r e a d w l = 5 d q s , d q s d q w r i t e ( b l 8 ) t o r e a d ( b c 4 / b l 8 ) n o p n o p c m d n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 t r p r e d o u t n n o p r e a d w l = 5 d q s , d q s w r i t e ( b c 4 ) t o r e a d ( b c 4 / b l 8 ) t w p s t b a n k c o l n w r i t e n o p n o p n o p n o p n o p n o p d q w r i t e b a n k c o l n n o p n o p b a n k c o l b d o u t n n o p n o p n o p n o p d o u t n + 4 d o u t n + 6 t w t r r l = 5 t b l = 4 t w p s t b a n k c o l b t w t r r l = 5
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 45 rev 1 . 2 0 1 / 200 9 write to write (wl=5, cwl=5, al=0) t 1 1 t 1 0 n o p d o u t n + 7 c k c k t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 n o p c m d n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 5 t c c d t w p r e t 1 2 n o p t 1 3 n o p w l = 5 d o u t b + 1 d o u t b + 2 w l = 5 d q s , d q s d q w r i t e ( b l 8 ) t o w r i t e ( b c 4 ) n o p t w p s t n o p c m d n o p n o p n o p a d d r e s s d o u t n + 1 d o u t n + 2 d o u t n + 3 t c c d t r p r e d o u t n n o p n o p w l = 5 r e a d d o u t b + 1 d o u t b + 2 d o u t b + 3 w l = 5 d q s , d q s w r i t e ( b c 4 ) t o w r i t e ( b l 8 ) t w p r e t w p s t t w p s t b a n k c o l n w r i t e n o p n o p n o p n o p n o p w r i t e d q w r i t e b a n k c o l n w r i t e b a n k c o l b n o p b a n k c o l b d o u t n n o p n o p n o p n o p d o u t n + 4 d o u t n + 6 d o u t b t b l = 4 t w r t w t r t b l = 4 t w r t w t r d o u t b + 3 d o u t b + 6 d o u t b + 7 d o u t b + 3 d o u t b + 5 d o u t b + 4 d o u t b
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 46 rev 1 . 2 0 1 / 200 9 self - refresh operation the self - refresh command can be used to retain data in the ddr3 sdram, even if the reset of the system is powere d down. when in the self - refresh mode, the ddr3 sdram retains data without external clocking. the ddr3 sdram device has a built - in timer to accommodate self - refresh operation. the self - refresh entry (sre) command is defined by having ?? , ??? , ??? , and ??? held low with we high at the rising edge of the clock. before issuing the self - refreshing - entry command, the ddr3 sdram must be idle with all bank precharge state with trp sat isfied. also, on - die termination must be turned off befor e issuing self - refresh - entry command, by either registering odt pin low odtl + 0.5tck prior to the self - refresh entry command or using mrs to mr1 command. once the self - refresh entry com mand is registered, cke must be held low to keep the device in self - refresh mode. during normal operation (dll on), mr1 (a0=0), the dll is automatically disabled upon entering self - refresh and is automatically enabled (including a dll - reset) upon exiting self - refresh. when the ddr3 sdram has entered self - refresh mode, al l of the external control signals, execpt cke and ????? , are don?t care. for proper self - refresh operation, all power supply and reference pins (vdd, vddq, vss, vssq, vrefca, and vrefdq) must be at valid levels. the dram initiates a minimum of one refres h command internally within tcke period once it enters self - refresh mode. the clock is internally disabled during self - refresh operation to save power. the minimum time that the ddr3 sdram must remain in self - refresh mode is tcke. the user may change the e xternal clock frequency or halt the external clock tcksre after self - refresh entry is registered; however, the clock must be restarted and stable tcksrx before the device can exit self - refresh mode. the procedure for exiting self - refresh requires a sequen ce of events. first, the clock must be stable prior to cke going back high. once a self - refresh exit command (srx, combination of cke going high and either nop or deselect on command bus) is registered, a delay of at least txs must be satisfied before a va lid command not requiring a locked dll can be issued to the device to allow for any internal refresh in progress. before a command which requires a locked dll can be applied, a delay of at least txsdll and applicable zqcal function requirements [tbd] must be satisfied. cke must remain high for the entire self - refresh exit period txsdll for proper operation except for self - refresh re - entry. upon exit from self - refresh, the ddr3 sdram can be put back into self - refresh mode after waiting at least txs period and issuing one refresh command (refresh period of trfc). nop or deselect commands must be registered on each positive clock edge during the self - refresh exit interval txs. odt must be turned off during txsdll. the use of self - refresh mode instructs the p ossibility that an internally times refresh event can be missed when cke is raised for exit from self - refresh mode. upon exit from self - refresh, the ddr3 sdram requires a minimum of one extra refresh com mand before it is put back into self - refresh mode.
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 47 rev 1 . 2 0 1 / 200 9 self - refresh entry/exit timing refresh command the refresh command (ref) is used during normal operation of the ddr3 sdrams. this command is not persistent, so it must be issued each time a refresh is required. the ddr3 sdram requires refresh cycles at a n average periodic interval of trefi. when ?? , ??? , and ??? are held low and we high at the rising edge of the clock, the chip enters a refresh cycle. all banks of the sdram must be precharged and idle for a minimum of the precharge time trp(min) before th e refresh command can be applied. the refresh addressing is generated by the internal refresh controller. this makes the address bits don?t care during a refresh command . an internal address counter suppliers the address during the refresh cycle. no cont rol of the exter nal address bus is required once this cycle has started. when the refresh cycle has completed, all banks of the sdram will be in the precharged (idle) state. a del ay between the refresh command and the next valid command, except nop or des , must be greater than or equal to the minimum refresh cycle time trfc(min) as shown in the following figure. in general, a refresh command needs to be issued to the ddr3 sdram regularly every trefi interval. to allow for improved efficiency in schedulin g and switching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of 8 refresh commands can be postponed during operation of the ddr3 sdram, meaning that at no point in time more than a total of 8 refresh commands are allowed to be postponed. in case that 8 refresh commands are postponed in a row, the result ing maximum interval between the surrounding refresh commands is limited to 9 x trefi. a maximum of 8 additional refresh commands can be issued in advance (pulled in), with each one reducing the number of regular refresh commands required later by one. note that pulling in more than 8 refresh commands in advance does not further reduce the number of regular refresh commands required la ter, so that the resulting max imum interval between two surrounding refresh command is limited to 9 x trefi. before entering self - refresh mode, all postponed refresh commands must be executed. ck , ck t 1 t 2 ta 0 tb 0 tc 0 tc 1 te 0 tf odtl tcksre t c k s r x tcpded trf sre nop valid 2 ) tckesr txsdll txs cmd odt note : 1 . only nop or des commands 2 . valid commands not requiring a locked dll 3 . valid commands requiring a locked dll t 0 td 0 valid cke nop srx nop 1 ) valid 3 ) valid valid valid valid enter self refresh exit self refresh do not care time break
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 48 rev 1 . 2 0 1 / 200 9 self - refresh entry/exit timing postponing refresh commands (example) pull ed - in refresh commands (example) ck ck t 0 t 1 ta 0 tb 0 tb 1 tb 3 ta 1 tb 2 nop cmd nop ref valid nop ref nop valid valid valid valid ref tc 0 tc 1 valid trfc trfc ( min ) trefi ( max , 9 x trefi ) dram must be idle dram must be idle time break 9 x trefi trefi trefi 8 ref - command postponed t 9 x trefi trefi t trefi 8 ref - commands pulled - in
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 49 rev 1 . 2 0 1 / 200 9 power - down modes power - down entry and exit power - down is synchronously entered when cke is registered low (along with nop or deselect command). cke is not allowed to go low while mode register set command, mpr op erations, zqcal operations, dll locking or read/write operation are in progress. cke is allowed to go low while any of other operation such as row activation, precharge or auto precharge and refresh are in prog ress, but power - down idd spec will not be appl ied until finishing those operation. the dll should be in a locked state when power - down is entered for fastest power - down exit timing. if the dll is not locked during power - down entry, the dll must be reset after exiting power - down mode for proper read op eration and synchronous odt operation. dram design provides all ac and dc timing and voltage specification as well proper dll operation with any cke intensive opera tions as long as dram controller complies with dram specifications. during power - down, if al l banks are closed after any in progress commands are completed, the device will be in precharge power - down mode; if any bank is open after in progress commands are completed, the device will be in active power - down mode. entering power - down deactivates t he input and output buffers, excluding ck, ck, odt, ??? , and ????? . to protect dram internal delay on cke line to block the input signals, multiple nop or deselect commands are needed during the cke switch off and cycl e(s) after, this timing period are def ined as tcpded. cke_low will result in deactivation of command and address receivers after tcpded has expired. power - down entry definitions status of dram mrs bit a12 dll pd exit relevant parameters active (a bank or more open) don't care on fast txp to a ny valid command. precharged (all banks precharged) 0 off slow txp to any valid command. since it is in precharge state, commands here will be act, ar, mrs/emrs, pr, or pra. txpdll to commands who need dll to operate, such as rd, rda, or odt control line. precharged (all banks precharged) 1 on fast txp to any valid command. also the dll is disabled upon entering precharge power - down (slow exit mode), but the dll is kept enabled during precharge power - down (fast exit mode) or active power - down. in power - d own mode, cke low, ????? high, and a stable clock signal must be maintained at the inputs of the ddr3 sdram, and odt should be in a valid state but all other input signals are don?t care ( if ????? goes low during power - down, the dram will be out of pd mode and into reset s tate). cke low must be maintain until tcke has been satisfied. power - down duration is limited by 9 times trefi of the device. the power - down state is synchronously exited when cke is registered high (along with a nop or deselect command). cke high must be maintained until tcke has been satisfied. a valid, executable command can be applied with power - down exit latency, txp and/or txpdll after cke goes high. power - down exit latency is defined at ac spec table of this datasheet.
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 50 rev 1 . 2 0 1 / 200 9 active power down entry and ex it timing diagram timing diagrams for cke with pd entry, pd exit with read, read with auto precharge, write and write with auto precharge, activate, precharge, refresh, mrs: power - down entry after read and read with auto precharge power - down en try after write with auto precharge t 0 t 1 t 2 ta 0 ta 1 tb 0 tb 1 tc 0 ck ck valid nop nop nop nop nop nop cmd cke valid valid tis tih tpd tih tis tcke address valid valid tcpded enter power - down exit power - down txp do not care time break t 0 t 1 ta 0 ta 1 ta 2 ta 3 ta 4 ta 5 ck ck rd or rda nop nop nop nop nop nop cmd cke address valid valid power - down entry do not care time break ta 6 ta 7 ta 8 tb 0 tb 1 nop nop nop nop nop valid valid tis tcpded dqs rl = al + cl din b din b + 1 din b + 2 din b + 3 din b + 4 din b + 5 din b + 6 din b + 7 din b din b + 1 din b + 2 din b + 3 trdpden bl 8 bc 4 tpd t 0 t 1 ta 0 ta 1 ta 2 ta 3 ta 4 ta 5 ck ck write nop nop nop nop nop nop cmd cke address bank , col n power - down entry do not care time break ta 6 ta 7 tb 0 tb 1 tb 2 nop nop nop nop nop nop tis tcpded dqs wl = al + cwl din b din b + 1 din b + 2 din b + 3 din b + 4 din b + 5 din b + 6 din b + 7 din b din b + 1 din b + 2 din b + 3 twrapden bl 8 bc 4 wr ( 1 ) tb 3 nop tc 0 valid tpd start internal precharge
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 51 rev 1 . 2 0 1 / 200 9 power - down entry after write precharge power - down (fast exit mode) entry and exit precharge power - down (slow exit mode) entry and exit refresh command to power - down entry t 0 t 1 t 2 t 3 t a 0 t a 1 c k c k r e f n o p n o p v a l i d c m d c k e d o n o t c a r e t i m e b r e a k n o p t i s t c p d e d v a l i d t p d v a l i d v a l i d t r e f p d e n a d d r e s s t 0 t 1 ta 0 ta 1 ta 2 ta 3 ta 4 ta 5 ck ck write nop nop nop nop nop nop cmd cke address bank , col n power - down entry do not care time break ta 6 ta 7 tb 0 tb 1 tb 2 nop nop nop nop nop nop tis tcpded dqs wl = al + cwl din b din b + 1 din b + 2 din b + 3 din b + 4 din b + 5 din b + 6 din b + 7 din b din b + 1 din b + 2 din b + 3 twrpden bl 8 bc 4 tc 0 nop tpd wr t 0 t 1 t 2 ta 0 ta 1 tb 0 tb 1 tc 0 ck ck write nop nop nop nop nop nop cmd cke do not care time break nop tis tcpded tih tcke tis txp nop valid tpd enter power - down mode exit power - down mode t 0 t 1 t 2 ta 0 ta 1 tb 0 tb 1 tc 0 ck ck write nop nop nop nop nop valid cmd cke do not care time break nop tis tcpded tih tcke tis txp nop valid tpd enter power - down mode exit power - down mode td 0 valid txpdll valid t 0 t 1 t 2 t 3 ta 0 ta 1 ck ck ref nop nop valid cmd cke do not care time break nop tis tcpded valid tpd valid valid trefpden address
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 52 rev 1 . 2 0 1 / 200 9 active command to power - down entry precharge/precharge all command to power - down entry mrs command to power - down entry t 0 t 1 t 2 t 3 ta 0 ta 1 ck ck active nop nop valid cmd cke do not care time break nop tis tcpded valid tpd valid valid tactpden address t 0 t 1 t 2 t 3 ta 0 ta 1 ck ck pre prea nop nop valid cmd cke do not care time break nop tis tcpded valid tpd valid valid tprepden address t 0 t 1 ta 0 ta 1 tb 0 tb 1 ck ck nop nop valid cmd cke do not care time break nop tis tcpded valid tpd valid tmrspden address mrs valid
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 53 rev 1 . 2 0 1 / 200 9 on - die termination (odt) odt (on - die termination) is a featur e of the ddr3 sdram that allows the dram to turn on/off termination resistance for each dq, dqs, ??? , and dm for x4 and x8 configuration (and tdqs, ???? for x8 configuration, when enabled via a11=1 in mr1) via the odt control pin. for x16 configuration, odt is applied to each dqu, dql, dqsu, ???? , dqsl, ???? , dmu, and dml signal via the odt control pi n. the odt feature is designed to improve signal integrity of the memory channel by allowing the dram controller to independently turn on/off termination resistance for any or all dram devices. the odt feature is turned off and not supported in self - refres h mode. a simple functional representation of the dram odt feature is shown as below. the switch is enabled by the internal odt control logic, which uses the external odt pin and other control information. the v alue of rtt is determined by the setti ngs of mode register bits. the odt pin will be ignored if the mode register mr1 and mr2 are programmed to disable odt and in self - refresh mode. odt mode register and odt truth table the odt mode is enabled if either of mr1 {a2, a6, a9} or mr2 {a9, a10} ar e non - zero. in this case, the value of rtt is deter mined by the settings of those bits. application: controller sends wr command together with odt asserted. one possible application: the rank that is being written to provides termination. dram turns on te rmination if it sees odt asserted (except odt is disabled by mr) dram does not use any write or read command decode information. termination truth table odt pin dram termination state 0 off 1 on, (off, if disabled by mr1 {a2, a6, a9} and mr2{a9, a10} in general) to other circuitry like rcv , ... vddq / 2 rtt switch dq , dqs , dm , tdqs odt
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 54 rev 1 . 2 0 1 / 200 9 synchronous odt mode synchronous odt mode is selected whenever the dll is turned on and locked. based on the power - down definition, these modes are: any bank active with cke high refresh with cke high idle mode with cke high active power down mode (regardless of mr0 bit a12) percharge power down mode if dll is enabled during precharge power down by mr0 bit a12 the direct odt feature is not supported during dll - off mode. the on - die termination resistors must be disabled by continu ously register ing the odt pin low and/or by programming the rtt_nom bits mr1{a9,a6,a2} to {0,0,0} via a mode register set command during dll - off mode. in synchronous odt mode, rtt will be turned on odtlon clock cycles after odt is sampled high by a rising clock edge and turned off odtloff clock cycles after odt is registered low by a rising clock edge. the odt latency is tied to the write latency (wl ) by: odtlonn = wl - 2; odtloff = wl - 2. odt latency and posted odt in synchronous odt mode, the additive latency (al) progr ammed into the mode register (mr1) also applies to the odt sig nal. the dram internal odt signal is delayed for a number of clock cycles defined by the additive latency (al) relative to the externa l odt signal. odtlon = cwl + al - 2; odtloff = cwl + al - 2 . for details, refer to ddr3 sdram latency definitions. odt latency symbol parameter ddr3 sdram unit odtlon odt turn on latency wl - 2 = cwl + al - 2 tck odtloff odt turn off latency wl - 2 = cwl + al - 2 tck timing parameters in synchronous odt mode, the following timing parameters apply: odtlon, odtloff, taon min/max, aof min/max. minimum rtt turn - on time (taon min) is the point in time when the device leaves high impedance and odt resistance begins to turn on. maximum rtt turn - on time (taon max) is the point in time when the odt resistance is fully on. both are measured from odtlon. minimum rtt turn - off time (taof min) is the point in time when the device starts to turn off the odt resistance. maximum rtt turn off time (taof max) is the point in time when the on - die termination has reached high impedance. both are measured from odtloff. when odt is asserted, it must remain high until odth4 is satisfied. if a write command is registered by the sdram with odt hi gh, then odt must remain high until odth4 (bl=4) or odth8 (bl=8) after the write command. odth4 and odth8 are measured from odt registered high to odt registered low or from the registration of a write command until odt is registered low.
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 55 rev 1 . 2 0 1 / 200 9 synchronous odt timing example for al=3; cwl=5; odtlon=al+ cwl - 2=6; odtloff=al+cwl - 2=6 synchronous odt example with bl=4, wl=7 odt must be held for at least odth4 after assertion (t1); odt must be kept high odth4 (bl=4) or odth8 (bl=8) after write command (t7). odth is measured from odt first registered high to odt first registered low, or from registration of write command with odt high to odt registered low. note that although odth4 is satisfied from odt registered at t6 odt must not go low before t11 as odth4 must also be satisfied from the registration of the write command at t7. odt during reads: as the ddr3 sdram cannot terminate and drive at the same time, rtt must be disabled at least half a clock cycle before the re ad preamble by driving the odt pin low appropriately. rtt may not be enabled until the end of the post - amble as shown in the following figure. dram turns on the termination when it stops driving which is determined by thz. if dram stops driving early (i.e. thz is early), then taonmin time may apply. if dram stops driving late (i.e thz is late), then dram complies with taonmax timing. note that odt may be disabled earlier before the read and enabled later after the read than shown in this example. odt must be disabled externally during reads by driving odt low. (example: cl=6; al=cl - 1=5; rl=al+cl =11; cwl=5; odtlon=cwl+al - 2=8; odtloff=cwl+al - 2=8) ck ck al = 3 t 11 t 10 t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 t 12 odt odth 4 , min odtlon = cwl + al - 2 odtloff = cwl + al - 2 t 13 t 14 t 15 cwl - 2 dram _ rtt taonmin taonmax taonmin taonmax rtt _ nom al = 3 transitioning do not care cke ck ck odth 4 t 11 t 10 t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 t 12 odt odtlon = cwl - 2 t 13 t 14 t 15 odtloff = wl - 2 dram _ rtt taonmin taonmax taofmax rtt _ nom t 16 t 17 t 18 odth 4 min odth 4 odtloff = cwl - 2 odtlon = cwl - 2 taofmin taofmax taonmax taonmin taofmin nop nop nop nop nop nop nop wrs 4 nop nop nop nop nop nop nop nop nop nop nop transitioning do not care ck ck t 11 t 10 t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 t 12 t 13 t 14 t 15 t 16 cmd address rl = al + cl rtt _ nom rtt odtloff = cwl + al - 2 taofmax taofmin odtlon = cwl + al - 2 rtt _ nom taonmax odt dram odt dqsdiff din b din b + 1 din b + 2 din b + 3 din b + 4 din b + 5 din b + 6 din b + 7 dq read nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop valid
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 56 rev 1 . 2 0 1 / 200 9 dynamic odt in certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination st rength of the ddr3 sdram can be changed without issuing an mrs command. this requirement is supported by the dynamic odt feature as described as follows: functional description the dynamic odt mode is enabled if bit (a9) or (a10) of mr2 is set to ?1?. the function is described as follows: two rtt values are availab le: rtt_nom and rtt_wr. the value for rtt_nom is preselected via bits a[9,6,2] in mr1. the value for rtt_wr is preselected via bits a[10,9] in mr2. during operation without write commands, the termination is controlled as follows: nominal termination stre ngth rtt_nom is selected. termination on/off timing is controlled via odt pin and latencies odtlon and odtloff. when a write command (wr, wra, wrs4, wrs8, wras4, wras8) is registered, and if dynamic odt is enabled, the termi nation is controlled as follows : a latency odtlcnw after the write command, termination strength rtt_wr is selected. a latency odtlcwn8 (for bl8, fixed by mrs or selected otf) or odtlcwn4 (for bc4, fixed by mrs or selected otf) after the write command, termination strength rtt_nom is s elected. termination on/off timing is controlled via odt pin and odtlon, odtloff. the following table shows latencies and timing parameters which are relevant for the on - die termination control in dynamic odt mode. the dynamic odt feature is not supported at dll - off mode. user must use mrs command to set rtt_wr, mr2[a10,a9 = [0,0], to disable dynamic odt externally. when odt is asserted, it must remain high until odth4 is satisfied. if a write command is registered by the sdram with odt hi gh, then odt must remain high until odth4 (bl=4) or odth8 (bl=8) after the write command. odth4 and odth8 are measured from odt registered high to odt registered low or from the registration of write command until odt is register low.
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 57 rev 1 . 2 0 1 / 200 9 latencies and timing parameters relev ant for dynamic odt name and description abbr. defined from defined to definition for all ddr3 speed pin unit odt turn - on latency odtlon registering external odt signal high turning termination on odtlon=wl - 2 tck odt turn - off latency odtloff registering external odt signal low turning termination off odtloff=wl - 2 tck odt latency for changing from rtt_nom to rtt_wr odtlcnw registering external write command change rtt strength from rtt_nom to rtt_wr odtlcnw=wl - 2 tck odt latency for change from rtt_wr to rtt_nom (bl=4) odtlcwn4 registering external write command change rtt strength from rtt_wr to rtt_nom odtlcwn4=4+odtloff tck odt latency for change from rtt_wr to rtt_nom (bl=8) odtlcwn8 registering external write command change rtt strength from rtt_wr t o rtt_nom odtlcwn8=6+odtloff tck(avg) minimum odt high time after odt assertion odth4 registering odt high odt registered low odth4=4 tck(avg) minimum odt high time after write (bl=4) odth4 registering write with odt high odt registered low odth4=4 tck( avg) minimum odt high time after write (bl=8) odth8 registering write with odt high odt register low odth8=6 tck(avg) rtt change skew tadc odtlcnw odtlcwn rtt valid tadc(min)=0.3tck(avg) tadc(max)=0.7tck(avg) tck(avg) note: taof,nom and tadc,nom are 0. 5tck (effectively adding half a clock cycle to odtloff, odtcnw, and odtlcwn) odt timing diagrams dynamic odt: behavior with odt being asserted before and after the write note: example for bc4 (via mrs or otf), al=0, cwl=5. odth4 applies to firs t registering odt high and to the registration of the write command. in tihs example odth4 would be satisfied if odt went low at t8. (4 clocks after the write command). ck ck t 11 t 10 t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 t 12 t 13 t 14 t 15 t 16 cmd odt rtt dqs / dqs dq odtlon odtlcwn 4 t 17 odtlcnw taonmin taonmax tadcmin tadcmax wl tadcmin tadcmax taofmin taofmax address rtt _ wr din n din n + 1 din n + 2 din n + 3 odth 4 odtloff nop nop nop nop wrs 4 nop nop nop nop nop nop nop nop nop nop nop nop nop valid odth 4 rtt _ nom do not care transitioning rtt _ nom
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 58 rev 1 . 2 0 1 / 200 9 dynamic odt: behavior without write command, al=0, cwl=5 note: odth4 is defined from odt registered high to odt registered low, so in this example odth4 is satisfied; odt regis tered low at t5 would also be legal. dynamic odt: behavior with odt pin being asserted together with write command for the duration of 6 clock cycles. note: exampl e for bl8 (via mrs or otf), al=0, cwl=5. in this example odth8=6 is exactly satisfied. tadcmax ck ck t 11 t 10 t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 cmd odt rtt dqs / dqs dq odtlon odtloff taonmin taonmax tadcmin rtt _ nom valid valid valid valid valid valid valid valid valid valid valid valid address odth 4 odtloff do not care transitioning taofmax taofmin ck ck t 11 t 10 t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 cmd odt rtt dqs / dqs dq odth 8 odtlon odtlcnw taonmin taonmax odtloff wl rtt _ wr nop wrs 8 nop nop nop nop nop nop nop nop nop nop valid din h din h + 1 din h + 2 din h + 3 din h + 4 din h + 5 din h + 6 din h + 7 odtlcwn 8 do not care transitioning address
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 59 rev 1 . 2 0 1 / 200 9 dynamic odt: behavior with odt pin being asserted together with write command for a duration of 6 clock cycles, example for bc4 (via mrs or otf), al=0, cwl=5. dynamic odt: behavior with odt pin being asserted t ogether with write command for the duration of 4 clock cycles. ck ck # t 11 t 10 t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 odt rtt dqs / dqs dq odtlon rtt _ wr odtlcnw taonmin taofmin taofmax taonmax odtloff wl odth 4 odtlcwn 4 cmd nop wrs 4 nop nop nop nop nop nop nop nop nop nop valid address din n din n + 1 din n + 2 din n + 3 do not care transitioning ck ck t 11 t 10 t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 odt rtt dqs / dqs dq odtlon rtt _ wr rtt _ nom odtlcnw taonmin tadcmin tadcmax taofmin taofmax taonmax odtloff wl odth 4 odtlcwn 4 cmd nop wrs 4 nop nop nop nop nop nop nop nop nop nop valid address din n din n + 1 din n + 2 din n + 3 do not care transitioning
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 60 rev 1 . 2 0 1 / 200 9 asynchronous odt mode asynchronous odt mode is selected when dram runs in dllon mode, but dll is temporarily disabled (i.e. frozen) in pre cha rge power - down (by mr0 bit a12). based on the power down mode definitions, this is currently precharge power down mode if dll is disabled during precharge power down by mr0 bit a12. in asynchronous odt timing mode, internal odt command is not delayed by ad ditive latency (al) relative to the external odt command. in asynchronous odt mode, the following timing parameters apply: taonpd min/max, taofpd min/max. minimum rtt turn - on time (taonpd min) is the point in time when the device termination circuit leav es high impedance state and odt resistance begins to turn on. maximum rtt turn on time (taonpd max) is the point in time when the odt resistance is fully on. taonpdmin and taonpdmax are measured from odt being sampled high. minimum rtt turn - off time (taofp dmin) is the point in time when the devices termination circuit starts to turn off the odt resis tance. maximum odt turn off time (taofpdmax) is the point in time when the on - die termination has reached high impedance. taofpdmin and taofpdmax are measured from odt being sample low. asynchronous odt timings on ddr3 sdram with fast odt transition: al is ignored. in precharge power down, odt receiver remains active, however no read or write command can be issued, as the respective add/cmd receivers may be disabled. asynchronous odt timing parameters for all speed bins symbol description min max unit taonpd asynchronous rtt turn - on delay (power - down with dll frozen) 1 9 ns taofpd asynchronous rtt turn - off delay (power - down with dll frozen) 1 9 ns odt timing parameters for power down (with dll frozen) entry and exit transition period description min max odt to rtt turn - on delay min{ odtlon * tck + taonmin; taonpdmin } min{ (wl - 2) * tck + taonmin; taonpdmin } max{ odtlon * tck + taonmax; taonpdmax } max{ (wl - 2) * tck + taonmax; taonpfmax } odt to rtt turn - off delay min{ odtloff * tck + taofmin; taofpdmin } min{ (wl - 2) * tck + taofmin; taofpdmin } max{ odtloff * tck + taofmax; taofpdmax } max{ (wl - 2) * tck + taofmax; taofpdmax } tanpd wl - 1 ck ck # t 11 t 10 t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 odt rtt taonpdmin cke tih tis t 12 t 13 t 14 t 15 taonpdmax taofpdmin taofpdmax tih tis do not care transitioning
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 61 rev 1 . 2 0 1 / 200 9 synchronous to asynchronous odt mode transition during power - down entry if dll is selected to be frozen in precharge power down mode by the setting of bit a12 in mr0 to 0, there is a transition p eriod around power down entry, where the ddr3 sdram may s how either synchronous or asynchronous odt behavior. the transition period is defined by the parameters tanpd and tcpded(min). tanpd is equal to (wl - 1) and is counted back wards in time from the clock cycle where cke is first registered low. tcpded(min) st arts with the clock cycle where cke is first registered low. the transition period begins with the starting point of tanpd and terminates at the end point of tcpded(min). if there is a r efresh command in progress while cke goes low, then the transition per iod ends at the later one of trfc(min) after the refresh command and the end point of tcpded(min). please note that the actual starting point at tanpd is excluded from the transition period, and the actual end point at tcpded(min) and trfc(min, respectivel y, are included in the transition period. odt assertion during the transition period may result in an rtt changes as early as the smaller of taonpdmin and (odt - lon*tck+taonmin) and as late as the larger of taonpdmax and (odtlon*tck+taonmax). odt de - asserti on during the transi tion period may result in an rtt change as early as the smaller of taofpdmin and (odtloff*tck+taofmin) and as late as the larger o f taofpdmax and (odtloff*tck+taofmax). note that, if al has a large value, the range where rtt is uncerta in becomes quite large. the following figure shows the three different cases: odt_a, synchronous behavior before tanpd; odt_b has a state change duri ng the transition period; odt_c shows a state change after the transition period. synchronous to asynchrono us transition during precharge power down (with dll frozen) entry (al=0; cwl=5; tanpd=wl - 1=4) ck ck cke cmd last sync . odt tanpd rtt sync . or async . odt odtloff taofmax taofmin taofpdmin taofpdmax odtloff + taofpdmin odtloff + taofpdmax rtt taofpdmin first async . odt rtt nop nop nop nop nop nop nop nop nop nop nop nop t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 pd entry transition period do not care time break transitioning tcpdedmin tcpded nop rtt rtt rtt taofpdmax
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 62 rev 1 . 2 0 1 / 200 9 asynchronous to synchronous odt mode transition during power - down exit if dll is selected to be frozen in precharge power down mode by the setting of bit a12 i n mr0 to 0, there is also a transition period around power down exit, where either synchronous or asynchronous response to a change in odt must be expected from the ddr3 sdram. this transition period starts tanpd before cke is first registered high, and ends txpdll after cke is first registered high. tanpd is equal to (wl - 1) and is counted (backwards) from the clock cycle where cke is first registered high. odt assertion during the transition period may result in an rtt change as early as the smaller of taonpdmin and (odt - lon*tck+taonmin) and as late as the larger of taonpdmax and (odtlon*tck+taonmax). odt de - assertion during the tran - sition period may result in an rtt change as early as the smaller of taofpdmin and (odtloff*tck+taofmin) and as late as th e larger of taofpdmax and (odtoff*tck+taofmax). note that if al has a large value, the range where rtt is uncertain becomes quite large. the following figure shows the three different cases: odt_c, asynchronous response before tanpd; odt_b has a state chan ge of odt during the transition period; odt_a shows a state change of odt after the transition period with synchronous response. asynchronous to synchronous transition during precharge power down (with dll frozen) exit (cl=6; al=cl - 1; cwl=5; tanpd=wl - 1=9) ck ck odt _ c _ sync dram _ rtt _ c _ sync odt _ b _ tran taofpdmax taofpdmin dram _ rtt _ b _ tran odt _ a _ async dram _ rtt _ a _ async t 0 t 1 t 2 ta 0 ta 1 ta 2 ta 3 ta 4 ta 5 ta 6 tb 0 tb 1 tb 2 tc 0 tc 1 tc 2 td 0 do not care time break transitioning td 1 cmd nop nop nop nop nop nop nop nop nop nop nop nop cke nop txpdll pd exit transition period rtt rtt taofpdmin odtloff + taofmax odtloff + taofmin taofpdmax tanpd nop taofmax rtt odtloff taofmin
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 63 rev 1 . 2 0 1 / 200 9 asynchronous to synchronous odt mode during short cke high and short cke low periods if the total time in precharge power down state or idle state is very short, the transition periods for pd entry and pd exit may overlap. in this case, the response of the ddr3 sdrams rtt to a change in odt state at the input may be synchronous or asynchronous from the state of the pd entry transition period to the end of the pd exit transition period (even if the entry ends later th an the exit period). if the total time in idle state is very short, the transition periods for pd exit and pd entry may overlap. in this case, the response of the ddr3 sdrams rtt to a change in odt state at the input may be synchronous or asynchronous from the state of the pd exit transition p eriod to the end of the pd entry transition period. note that in the following figure, it is assumed that there was no refres h command in progress when idle state was entered. transition period for short cke cycles with entry and exit period overlapping (al=0; wl=5; tanpd=wl - 1=4) zq calibration commands zq calibration description zq calibration command is used to calibrate dram ron and odt values. ddr3 sdram needs longer time to calibrate output driver and on - die termination circuits at initialization an d relatively smaller time to perform periodic calibrations. zqcl command is used to perform the initial calibration during power - up initialization sequence. this command may be issued at any time by the controller depending on the system environment. zqcl command triggers the calibration engine inside the dram and once calibration is achieved the calibrated values are transferred from calibration engine to dram io which gets reflected as updated output driver and on - die termination values. the first zqcl co mmand issued after reset is allowed a timing period of tzqinit to perform the full calibration and the transfer of values. all other zqcl commands except the first zqcl command issued after reset is allowed a timing period of tzqoper. zqcs command is used to perform periodic calibrations to account for voltage and temperature variations. a shorter timing win dow is provided to perform the calibration and transfer of values as defined by timing parameter tzqcs. no other activities should be performed on the dram channel by the controller for the duration of tzqinit, tzqoper, or tzqcs. the quiet time on the dram channel allows calibration of output driver and on - die termination values. once dram calibration is achieved, the dram should disable zq current consu mption path to reduce power. all banks must be precharged and trp met before zqcl or zqcs commands are issued by the controller. zq calibration commands can also be issued in parallel to dll lock time when coming out of self refresh. upon self - refresh exi t, ddr3 sdram will not perform an io calibration without an explicit zq calibration command. the earliest possible time for zq calibr ation command (short or long) after self refresh exit is txs. in systems that share the zq resistor between devices, the co ntroller must not allow any overlap of tzqoper, tzqinit, or tzqcs between ranks. ck ck t 11 t 10 t 0 t 1 t 3 t 5 t 6 t 7 t 9 t 2 t 4 t 8 t 12 t 13 t 14 tanpd do not care transitioning cke cmd ref nop nop nop nop nop nop nop nop nop nop nop nop nop nop pd exit transition period tanpd txpdll pd entry transition period trfc ( min ) cke short cke high transition period txpdll
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 64 rev 1 . 2 0 1 / 200 9 zq calibration timing note: 1. cke must be continuously registered high during the calibration procedure. 2. on - die termination must be disabled via the odt signal or mrs du ring the calibration procedure. 3. all devices connected to the dq bus should be high impedance during the calibration procedure. zq external resistor value, tolerance, and capacitive loading in order to use the zq calibration function, a 240 ohm +/ - 0.1% tolerance external resistor connected between the zq pin and ground. the single resistor can be used for each sdram or one resistor can be shared between two sdrams if the zq calibra tion timings for each sdram do not overlap. the total capacitive loading on the zq pin must be limited. absolute maximum ratings absolute maximum dc ratings symbol parameter rating units note vdd voltage on vdd pin relative to vss - 0.4 ~ 1.975 v 1,3 vddq voltage on vddq pin relative to vss - 0.4 ~ 1.975 v 1,3 vin, vout vol tage on any pin relative to vss - 0.4 ~ 1.975 v 1 tstg storage temperature - 55 ~ 100 ? ck ck tc 2 t 0 t 1 ta 1 ta 3 tb 0 tb 1 tc 1 ta 0 ta 2 tc 0 address cmd zqcl nop nop nop valid valid zqcs nop nop nop valid odt tzqcs valid valid valid valid valid a 10 cke valid valid valid valid valid valid ( 1 ) ( 2 ) ( 1 ) ( 2 ) dq bus hi - z activities hi - z activities tzqcs ( 3 ) ( 3 ) do not care time break
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 65 rev 1 . 2 0 1 / 200 9 temperature range symbol parameter rating units notes toper normal operating temperature range 0 to 85 ? c 1,2 extended temperature range 85 to 95 ? c 1,3 note: 1. operating temperature toper is the case surface temperature on the center/top side of the dram. 2. the normal temperature range specifies the temperatures where all dram specification will be supported. during operation, the dram case temperature must be maintained between 0 - 85 ? c under all operating conditions. 3. some applications require operation of the dram in the extended temperature range between 85 ? c and 95 ? c case temperature. full specifications are guaranteed in this range, but the following additional apply: a) refresh commands must be doubled in frequency, therefore, redu cing the refresh interval trefi to 3.9us. it is also possible to specify a component with 1x refresh (trefi to 7.8us) in the extended temperature range. b) if self - refresh operation is required in the extended temperature range, then it is mandatory to ei ther use the manual self - refresh mode with extended temperature range capability (mr2 a6=0 and mr2 a7=1) or enable the optional auto self - refresh mode (mr2 a6=1 and mr2 a7=0). ac & dc operating conditions recommended dc operating conditions symbol param eter rating unit note min. typ. max. vdd supply voltage 1.425 1.5 1.575 v 1,2 vddq supply voltage for output 1.425 1.5 1.575 v 1,2 note: 1. under all conditions vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters are meas ured with vdd and vddq tied together.
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 66 rev 1 . 2 0 1 / 200 9 ac & dc input measurement levels ac and dc logic input levels for single - ended signals & command and address symbol parameter ddr3 - 800/ 1066 ddr3 - 1333 /1600 unit note min. max. min. max. vih.ca(dc) dc input log ic high vref + 0.100 vdd vref + 0.100 vdd v 1 vil.ca(dc) dc input logic low vss vref - 0.100 vss vref - 0.100 v 1 vih.ca(ac) ac input logic high vref + 0.175 note2 vref + 0.175 note2 v 1,2 vil.ca(ac) ac input logic low note2 vref - 0.175 note2 vref - 0. 175 v 1,2 vih.ca(ac150) ac input logic high - - vref + 0.150 note2 v 1,2 vil.ca(ac150) ac input logic low - - - vref - 0.150 v 1,2 vrefca(dc) reference voltage for add, cmd inputs 0.49 * vdd 0.51 * vdd 0.49 * vdd 0.51 * vdd v 3,4 note: 1. for input onl y pins except reset.vre f =vrefca(dc) 2. see "overshoot and undershoot specifications" 3. the ac peak noise on vref may not allow vref to deviate from vref(dc) by more than +/ - 0.1% vdd. 4. for reference: approx. vdd/2 +/ - 15mv. ac and dc logic input lev els for single - ended signals & dq and dm symbol parameter ddr3 - 1066 ddr3 - 1333 unit note min. max. min. max. vih.dq(dc) dc input logic high vref + 0.100 vdd vref + 0.100 vdd v 1 vil.dq(dc) dc input logic low vss vref - 0.100 vss vref - 0.100 v 1 vih .dq(ac) ac input logic high vref + 0.175 note2 vref + 0.150 note2 v 1,2,5 vil.dq(ac) ac input logic low note2 vref - 0.175 note2 vref - 0.150 v 1,2,5 vrefdq(dc) reference voltage for dq, dm inputs 0.49 * vdd 0.51 * vdd 0.49 * vdd 0.51 * vdd v 3,4 note: 1. for input only pins except reset.vre=vref dq (dc) 2. see "overshoot and undershoot specifications" 3. the ac peak noise on vref may not allow vref to deviate from vref(dc) by more than +/ - 0.1% vdd. 4. for reference: approx. vdd/2 +/ - 15mv. 5. single - en ded swing requirement for dqs, dqs is 350mv (peak to peak). differential swing requirement for dqs, dqs is 700mv (peak to peak)
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 67 rev 1 . 2 0 1 / 200 9 vref tolerances the dc - tolerance limits and ac - moist limits for the reference voltages vrefca and vrefdq are illustrated in t he following figure. it shows a valid reference voltage vref(t) as a function of time. (vref stands for vrefca and vrefdq likewise). vref(dc) is the linear average of vref(t) over a very long period of time (e.g.,1 sec). this average has to meet the min/ma x requirement in previous page. furthermore vref(t) may temporarily deviate from vref(dc) by no more than +/ - 1% vdd. the voltage levels for setup and hold time measurements vih(ac), vih(dc), vil(ac), and vil(dc) are dependent on vref. vref shall be under stood as vref(dc). the clarifies that dc - variations of vref affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. system timing and voltage budgets need to account for vref(dc) devi ations from the optimum position within the data - eye of the input signals. this also clarifies that the dram setup/hold specification and derating values need to include time and voltage associated wi th vref ac - noise. timing and voltage effects due to ac - noise on vref up to the specified limit (+/ - 1% of vdd) are included in dram timing and their associated deratings. illustration of vref(dc) tolerance and vref ac - noise limits ac and dc logic input levels for differential sign als symbol parameter min. max. unit notes vihdiff differential input logic high 0.2 note3 v 1 vildiff differential input logic low note3 - 0.2 v 1 vihdiff(ac) differential input high ac 2 x (vih(ac) - vref) note3 v 2 vildiff(ac) differential input low a c note3 2 x (vref - vil(ac)) v 2 note: 1. used to define a differential signal slew - rate. 2. for ck - ck use vih/vil(ac) of add/cmd and vrefca; for dqs - dqs, dqsl, dqsl, dqsu, dqsu use vih/vil(ac) of dqs and vrefdq; if a reduced ac - high or ac - low level i s used for a signal group, then the reduced level applies also there. 3. these values are not defined, however the single - ended signals ck, ck, dqs, dqs, dqsl, dqsl, dqsu, dqsu need to be within the respective limits (vih(dc)max, vil(dc)min) for single - end ed signals as we l l as limitations for overshoot and undershoot. vref ( dc ) vref ( dc ) max vref ( dc ) min vdd / 2 vref ac - noise voltage time vdd vss
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 68 rev 1 . 2 0 1 / 200 9 definition of differential ac - swing and time above ac - level allowed time before ringback (tdvac) for ck - ?? ??? slew rate [v/ns] tdvac [ps] @ivi h/ldiff(ac)i = 350mv tdvac [ps] @ivih/ldiff(ac)i = 300mv min max min max > 4.0 75 - 175 - 4 57 - 170 - 3 50 - 167 - 2 38 - 163 - 1.8 34 - 162 - 1.6 29 - 161 - 1.4 22 - 159 - 1.2 13 - 155 - 1 0 - 150 - < 1.0 0 - 150 - single - ended requirements for differential signals each individual component of a differential signal (ck, dqs, dqsl, dqsu, ?? , ??? , ???? , or ???? ) has also to comply with certain requirements for single - ended signals. ck and ?? have to approximately reach vsehmin / vselmax (approximately equal to the ac - levels (vih(ac) / vil(ac)) for add/cmd signals) in every half - cycle. dqs, dqsl, dqsu, dqs, dqsl, dqsl have to reach vsehmin / vselmax (approxi mately the ac - levels (vih(ac) / vil(ac)) for dq signals) in every half - cycle proceeding and following a valid transition. time d i f f e r e n t i a l i n p u t v o l t a g e ( i . e . d q s C d q s , c k C c k ) tdvac tdvac half cycle vih . diff . ac . min vih . diff. dc min vil . diff . ac . max 0 vil . diff. dc max
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 69 rev 1 . 2 0 1 / 200 9 single - ended levels for ck, dqs, dqsl, dqsu, ?? ??? ???? ???? ? symbol parameter min max unit notes vseh single - ended high - level for strobes (vddq/2) + 0.175 note3 v 1, 2 single - ended high - level for ck, ck (vddq/2) + 0.175 note3 v 1, 2 vsel single - ended low - level for strobes note3 (vddq/2) - 0.175 v 1, 2 si ngle - ended low - level for ck, ck note3 (vddq/2) - 0.175 v 1, 2 note: 1. for ck, ck use vih/vil(ac) of add/cmd; for strobes (dqs, dqsl, dqsu, ck, dqs, dqsl, or dqsu) use vih/vil(ac) of dqs. 2. vih(ac)/vil(ac) for dqs is based on vrefdq; vih(ac)/vil(ac) for add/cmd is based on vrefca; if a reduced ac - high or ac - low level is used for a signal group, then the reduced level applies also there. 3. these values are not defined, however the single - ended signals ck, ck, dqs, dqs, dqsl, dqsl, dqsu, dqsu need to be w ithin the respective limits (vih(dc)max, vil(dc)min) for single - ended signals as well as limitations for overshoot and undershoot. differential input cross point voltage to guarantee tight setup and hold times as well as output skew parameters with respe ct to clock and strobe, each cross point voltage of differential input signals (ck, ck and dqs, dqs) must meet the requirements in the following table. the differential input cross point voltage vix is measured from the actual cross point of true and compl etement signal to the midlevel between of vdd and vss. vix definition cross point voltage for differential input signals (ck, dqs) symbol parameter min. max. unit note vix differential input cross point voltage relative to vdd/2 for ck, ck - 1 50 150 mv - 175 175 mv 1 differential input cross point voltage relative to vdd/2 for dqs, dqs - 150 150 mv note1: extended range for vix is only allowed for clock and if single - ended clock input signals ck and ck are monotonic with a single - ended swing vsel / vseh of at least vdd/2 250mv, and when the differential slew rate of ck - ck is larger than 3v/ns.
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 70 rev 1 . 2 0 1 / 200 9 slew rate definition for differential input signals differential input slew rate definition description measured defined by from to differential input slew rate for rising edge (ck - ck & dqs - dqs) vildiffmax vihdiffmin [vihdiffmin - vildiffmax] / deltatrdiff differential input slew rate for falling edge (ck - ck & dqs - dqs) vihdiffmin vildiffmax [vihdiffmin - vildiffmax] / deltatfdiff the differential si gnal (i.e., ck - ck & dqs - dqs) must be linear between these thresholds. input nominal slew rate definition for single ended signals delta tfdiff delta trdiff vihdiffmin vildiffmax 0
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 71 rev 1 . 2 0 1 / 200 9 ac and dc output measurement levels single ended ac and dc output levels symbol parameter value unit notes vo h(dc) dc output high measurement level (for iv curve linearity) 0.8xvddq v vom(dc) dc output mid measurement level (for iv curve linearity) 0.5xvddq v vol(dc) dc output low measurement level (fro iv curve linearity) 0.2xvddq v voh(ac) ac output high measurement level (for output sr) vtt+0.1xvddq v 1 vol(ac) ac output lo w measurement level (for output sr) vtt - 0.1xvddq v 1 note: 1. the swing of 0.1 x vddq is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to vtt = vddq/2. differential ac and dc output levels symbol parameter ddr3 unit notes vohdiff(ac) ac differential output high measurement level (for output sr) +0.2 x vddq v 1 voldiff(ac) ac differential output low measurement level (for output sr) - 0.2 x vddq v 1 not e: 1. the swing of 0.2 x vddq is based on approximately 50% of the static differential output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to vtt=vddq/2 at each of the differential outputs. single ended output slew rate description measured defined by from to single ended output slew rate for rising edge vol(ac) voh(ac) [voh(ac) - vol(ac)] / deltatrs e single ended output slew rate for falling edge voh(ac) vol(ac) [voh(ac) - vol(ac)] / deltatfse note: output slew rate is verified by design and characterization, and may not be subject to production test. single ended output slew rate definition delta tfse delta trse voh ( ac ) vol ( ac ) vtt
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 72 rev 1 . 2 0 1 / 200 9 output slew rate (single - ended) parameter symbol ddr3 - 800 ( - ac/ - ad ) ddr3 - 1066 ( - be/ - b f ) ddr3 - 1 333 ( - cf/ - cg ) ddr3 - 1 600 ( - dg/ - dh ) unit min. max. min. max. max. max. min. max. single - ended output slew rate srqse 2.5 5 2. 5 5 2. 5 5 tbd 5 v/ns note: sr: slew rate. q: query output (like in dq, which stands for data - in, query - output). se: single - ended signals. for ron = rzq/7 setting . differential output slew rate description measured defined by from to differential output slew rate for rising edge voldiff(ac) vohdiff(ac) [vohdiff(ac) - voldiff(ac)] / deltatrdiff differential output slew rate for falling edge vohdiff(ac) voldi ff(ac) [vohdiff(ac) - voldiff(ac)] / deltatfdiff note: output slew rate is verified by design and characterization, and may not be subject to production test. differential output slew rate definition differential output slew rate symbol parameter ddr3 - 800 ( - ac/ - ad) ddr3 - 1066 ( - be / - bf ) ddr3 - 1 333 ( - cf/ cg) ddr3 - 1 600 ( - dg/ - dh ) units min. max. min. max. min. max. min. max. srqdiff differential output slew rate 5 10 5 10 5 10 tbd 10 v/ns note: sr: slew rate. q: query output (like in dq, which stands for data - in, query - output). diff: differential signals. for ron = rzq/7 setting. delta tfdiff delta trdiff vohdiff ( ac ) voldiff ( ac ) 0
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 73 rev 1 . 2 0 1 / 200 9 reference load for ac timing and output slew rate the following figure represents the effective reference load of 25 ohms used in defining the relevant ac ti ming parameters of the device as well as output slew rate measurements. it is not intended as a precise representation of any particular system environment or a depiction of the actual load present ed by a production tester. system designers should use ibis or other simulation tools to correlate the timing reference load to a sys tem environment. manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines te rminated at the tester electronics. 25 ohm vtt = vddq / 2 ck, ck dut timing reference points vddq dq dqs dqs rdqs rdqs
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 74 rev 1 . 2 0 1 / 200 9 overshoot and undershoot specifications ac overshoot/undershoot specification for address and control pins (a0 - a13, ba0 - ba2, ?? , ??? , ??? , ?? , cke, odt item ddr3 - 800 ddr3 - 1066 ddr3 - 1333 ddr3 - 1600 units maximum peak amplitude allowed for overshoot area 0.4 0.4 0.4 0 .4 v maximum peak amplitude allowed for undershoot area 0.4 0.4 0.4 0.4 v maximum overshoot area above vdd 0.67 0.5 0.4 0.33 v - ns maximum undershoot area below vss 0.67 0.5 0.4 0.33 v - ns ac overshoot/undershoot specificat ion for clock, data, strobe, and mask (ck, ?? , dq, ??? , dqs, dm) item ddr3 - 800 ddr3 - 1066 ddr3 - 1333 ddr3 - 1600 units maximum peak amplitude allowed for overshoot area 0.4 0.4 0.4 0.4 v maximum peak amplitude allowed for undershoot area 0.4 0.4 0.4 0.4 v maximum overshoot area above vdd 0. 25 0.19 0 . 15 0.13 v - ns maximum undershoot area below vss 0.25 0.19 0.15 0.13 v - ns vdd vss overshoot area undershoot area maximum amplitude maximum amplitude time (ns) volts (v) vddq vssq overshoot area undershoot area maximum amplitude maximum amplitude time (ns) volts (v)
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 75 rev 1 . 2 0 1 / 200 9 34 ohm output driver dc electrical characteristics a functional representation of the output buffer is shown as below. output driver impedance ron is defined by the value of the external reference resistor rzq as follows: ron 34 = r zq / 7 (nominal 34.4ohms +/ - 10% with nominal r zq =240ohms) the individual pull - up and pull - down resistors (ron pu and ron pd ) are defined as follows: ron pu = [vddq - vout] / l iou t l ------------------- under the condition that ron pd is turned off (1) ron pd = vout / i iout i ------------------------------- under the condition that ron pu is turned off (2) output driver dc electrical characteristics, assum ing r zq = 240ohms; entire operating temperature range; after proper zq calibration ron nom resistor vout min nom max unit notes 34 ohms ron 34pd voldc = 0.2 x vddq 0.6 1 1.1 r zq / 7 1,2,3 vomdc = 0.5 x vddq 0.9 1 1.1 r zq / 7 1,2,3 vohdc = 0.8 x vddq 0 .9 1 1.4 r zq / 7 1,2,3 ron 34pu voldc = 0.2 x vddq 0.9 1 1.4 r zq / 7 1,2,3 vomdc = 0.5 x vddq 0.9 1 1.1 r zq / 7 1,2,3 vohdc = 0.8 x vddq 0.6 1 1.1 r zq / 7 1,2,3 mismatch between pull - up and pull - down, mmpupd vomdc = 0.5 x vddq - 10 10 % 1,2,4 not e: 1. the tolerance limits are specified after calibration with stable voltage and temperature. for the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 2. the tolerance limits are specified under the condition that vddq = vdd and that vssq = vss. 3. pull - down and pull - up output driver impedances are recommended to be calibrated at 0.5 x vddq. other calibration schemes may be used to achieve the linearity spe c shown above. e.g. calibration at 0.2 x vddq and 0.8 x vddq. 4. measurement definition for mismatch between pull - up and pull - down, mmpupd: measure ronpu and ronpd, but at 0.5 x vddq: mmpupd = [ronpu - ronpd] / ronnom x 100 to other circuitry like rcv , ... ron ron pu pd i pu i pd vddq vssq dq i out v out output driver chip in drive mode
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 76 rev 1 . 2 0 1 / 200 9 output driver temperature and voltage sensitivity if temperature and/or voltage after calibration, the tolerance limits widen according to the following table. delta t = t - t(@calibration); delta v = vddq - vddq(@calibration); vdd = vddq note: dr on dt and dr on dv are not subject to pro duction test but are verified by design and characterization. items m in . m ax . unit ronpu@vohdc 0.6 - dr on dth*ldelta tl - dr on dvh*ldelta vl 1.1 + dr on dth*ldelta tl - dr on dvh*ldelta vl r zq /7 ron@vomdc 0.9 - dr on dtm*ldelta tl - dr on dvm*ldelta vl 1.1 + dr on d tm*ldelta tl - dr on dvm*ldelta vl r zq /7 ronpd@voldc 0.6 - dr on dtl*ldelta tl - dr on dvl*ldelta vl 1.1 + dr on dtl*ldelta tl - dr on dvl*ldelta vl r zq /7 output driver voltage and temperature sensitivity items m in . m ax unit drondtm 0 1.5 %/ ? c drondvm 0 0.15 %/mv drondtl 0 1.5 %/ ? c drondvl 0 tbd %/mv drondth 0 1.5 %/ ? c drondvh 0 tbd %/mv note: these parameters may not be subject to production test. they are verified by design and characterization.
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 77 rev 1 . 2 0 1 / 200 9 on - die termination (odt) levels and i - v characteristics on - die termination effective resistance rtt is defined by bits a9, a6, and a2 of the mr1 register. odt is applied to the dq, dm, dqs/dqs, and tdqs/tdqs (x8 devices only) pins. a functional represent ation of the on - die termination is shown in the following figure. the individual pull - up and pull - down resistors (rtt pu and rtt pd ) are defined as follows: rtt pu = [vddq - vout] / i iout i ------------------ under the condition that rtt pd is turned off (3) rtt pd = vout / i iout i ------------------------------ under the condition that rtt pu is turned off (4) odt dc electrical characteristics the following table provides an overview of the odt dc electrical characteristics. the values for rtt 60 pd120 , rtt 60pu120 , rtt 120pd240 , rtt 120pu240 , rtt 40pd80 , rtt 40pu80 , rtt 30pd60 , rtt 30pu60 , rtt 20pd40 , rtt 20pu40 are not specification requirements, but can be used as design guide lines: odt dc electrical characteristics, assuming r zq = 240ohms +/ - 1% entir e operating temperature range; after proper zq calibration mr1 a9, a6, a2 rtt resistor vout min nom max unit notes 0,1,0 120 ? rtt 120pd240 voldc = 0.2 x vddq 0.6 1 1.1 r zq 1,2,3,4 0.5 x vddq 0.9 1 1.1 r zq 1,2,3,4 vohdc = 0.8 x vddq 0.9 1 1.4 r zq 1 ,2,3,4 rtt 120pu240 voldc = 0.2 x vddq 0.9 1 1.4 r zq 1,2,3,4 0.5 x vddq 0.9 1 1,1 r zq 1,2,3,4 vohdc = 0.8 x vddq 0.6 1 1.1 r zq 1,2,3,4 rtt 120 vil(ac) to vih(ac) 0.9 1 1.6 r zq /2 1,2,5 to other circuitry like rcv , ... rtt rtt pu pd i pu i pd vddq vssq dq i out v out odt chip in termination mode i = i - i out pd pu
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 78 rev 1 . 2 0 1 / 200 9 0, 0, 1 60 ? rtt 60pd120 voldc = 0.2 x vddq 0.6 1 1.1 rzq/2 1,2,3,4 0.5 x vddq 0.9 1 1.1 rzq/2 1,2,3,4 vohdc = 0.8 x vddq 0.9 1 1.4 rzq/2 1,2,3,4 rtt 60pu120 voldc = 0.2 x vddq 0.9 1 1.4 rzq/2 1,2,3,4 0.5 x vddq 0.9 1 1.1 rzq/2 1,2,3,4 vohdc = 0.8 x vddq 0.6 1 1.1 rzq/2 1,2,3,4 rtt 60 vil(ac) to vih(ac) 0.9 1 1.6 rzq/4 1,2,5 0, 1, 1 40 ? rtt 40pd80 voldc = 0.2 x vddq 0.6 1 1.1 rzq/3 1,2,3,4 0.5 x vddq 0.9 1 1.1 rzq/3 1,2,3,4 vohdc = 0.8 x vddq 0.9 1 1.4 rzq/3 1,2,3,4 rtt40pu80 voldc = 0.2 x vddq 0.9 1 1.4 rzq/3 1,2,3,4 0.5 x vddq 0.9 1 1.1 rzq/3 1,2,3,4 vohdc = 0.8 x vd dq 0.6 1 1.1 rzq/3 1,2,3,4 rtt40 vil(ac) to vih(ac) 0.9 1 1.6 rzq/6 1,2,5 1, 0, 1 30 ? rtt30pd60 voldc = 0.2 x vddq 0.6 1 1.1 rzq/4 1,2,3,4 0.5 x vddq 0.9 1 1.1 rzq/4 1,2,3,4 vohdc = 0.8 x vddq 0.9 1 1.4 rzq/4 1,2,3,4 rtt30pu60 voldc = 0.2 x vddq 0.9 1 1.4 rzq/4 1,2,3,4 0.5 x vddq 0.9 1 1.1 rzq/4 1,2,3,4 vohdc = 0.8 x vddq 0.6 1 1.1 rzq/4 1,2,3,4 rtt30 vil(ac) to vih(ac) 0.9 1 1.6 rzq/8 1,2,5 1, 0, 0 20 ? rtt20pd40 voldc = 0.2 x vddq 0.6 1 1.1 rzq/6 1,2,3,4 0.5 x vddq 0.9 1 1.1 rzq/6 1,2,3,4 vohdc = 0.8 x vddq 0.9 1 1.4 rzq/6 1,2,3,4 rtt20pu40 voldc = 0.2 x vddq 0.9 1 1.4 rzq/6 1,2,3,4 0.5 x vddq 0.9 1 1.1 rzq/6 1,2,3,4 vohdc = 0.8 x vddq 0.6 1 1.1 rzq/6 1,2,3,4 rtt20 vil(ac) to vih(ac) 0.9 1 1.6 rzq/12 1,2,5 d eviation of vm w.r.t. vddq/2, dvm - 5 + 5 % 1,2,5,6 note: 1. the tolerance limits are specified after calibration with stable voltage and temperature. for the behavior of the toleranc e limits if tempera ture or voltage changes after calibration, see following section on voltage and temperat ure sensitivity. 2. the tolerance limits are specified under the condition that vddq = vdd and that vssq = vss. 3. pull - down and pull - up odt resistors are recommended to be calibrated at 0.5 x vddq. other calibration may be used to achieve the lin earity s pec shown above. 4. not a specification requirement, but a design guide line. 5. measurement definition for rtt: apply vih(ac) to pin under test and measure current / (vih(ac)), then apply vil(ac) to pin under test and measure current / ( vil(ac)) respec ti vely. rtt = [vih(ac) - vil(ac)] / [i(vih(ac)) - i(vil(ac))] 6. measurement definition for v m and dv m : measure voltage (v m ) at test pin (midpoint) with no lead: delta v m = [2v m / vddq - 1] x 100
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 79 rev 1 . 2 0 1 / 200 9 odt temperature and voltage sensitivity if temperature and/ or voltage after calibration, the tolerance limits widen according to the following table. delta t = t - t(@calibration); delta v = vddq - vddq(@calibration); vdd = vddq odt sensitivity definition min max unit rtt 0.9 - drttdt*ldelta tl - drttdv*ldelta vl 1.6 + drttdt*ldelta tl - drttdv*ldelta vl rzq/2,4,6,8,12 odt voltage and temperature sensitivity min max unit drttdt 0 1.5 %/ ? c drttdv 0 0.15 %/mv note: these parameters may not be subject to production test. they are verified by design and charac terization. test load for odt timings different than for timing measurements, the reference load for odt timings is defined in the following figure. odt timing definitions definitions for t aon , t aonpd , t aof , t aofpd , and t adc are provided in the follo wing table and subsequent figures. symbol begin point definition end point definition taon rising edge of ck - ck defined by the end point of odtlon extrapolated point at vssq taonpd rising edge of ck - ck with odt being first registered high extrapolat ed point at vssq taof rising edge of ck - ck defined by the end point of odtloff end point: extrapolated point at vrtt_nom taofpd rising edge of ck - ck with odt being first registered low end point: extrapolated point at vrtt_nom tadc rising edge of ck - ck defined by the end point of odtlcnw, odtlcwn4, or odtlcwn8 end point: extrapolated point at vrtt_wr and vrtt_nom respectively reference settings for odt timing measurements measured parameter rtt_nom setting rtt_wr setting vsw1[v] vsw2[v] taon rzq/ 4 na 0.05 0.1 rzq/12 na 0.1 0.2 taonpd rzq/4 na 0.05 0.1 rzq/12 na 0.1 0.2 taof rzq/4 na 0.05 0.1 rzq/12 na 0.1 0.2 taofpd rzq/4 na 0.05 0.1 rzq/12 na 0.1 0.2 tadc rzq/12 rzq/2 0.2 0.3 25ohm vtt = vssq dut timing reference points vddq dq dqs dqs rdqs rdqs vssq
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 80 rev 1 . 2 0 1 / 200 9 definition of t aon definition of t aonpd definition of t aof taon tsw 2 tsw 1 vsw 1 vsw 2 vssq vtt dq , dm dqs , dqs # tdqs , tdqs # end point : extrapolated point at vssq ck ck # begin point : rising edge of ck C ck # defined by the end point of odtlon taonpd tsw 2 tsw 1 vsw 1 vsw 2 vssq vtt dq , dm dqs , dqs # tdqs , tdqs # end point : extrapolated point at vssq ck ck # begin point : rising edge of ck C ck # with odt being first register high taof tsw 2 tsw 1 vsw 1 vsw 2 vssq vtt dq , dm dqs , dqs # tdqs , tdqs # end point : extrapolated point at vrtt _ nom ck ck # begin point : rising edge of ck C ck # defined by the end point of odtloff vrtt _ nom
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 81 rev 1 . 2 0 1 / 200 9 definition of t aofpd definition of t adc taofpd tsw 2 tsw 1 vsw 1 vsw 2 vssq vtt dq , dm dqs , dqs # tdqs , tdqs # end point : extrapolated point at vrtt _ nom ck ck # begin point : rising edge of ck C ck # with odt being first registered low vrtt _ nom tadc tsw 21 tsw 11 vsw 1 vsw 2 dq , dm dqs , dqs # tdqs , tdqs # end point : extrapolated point at vrtt _ nom ck ck # begin point : rising edge of ck C ck # defined by the end of odtlcnw vrtt _ nom tadc tsw 22 tsw 12 vssq vtt end point : extrapolated point at vrtt _ wr ck ck # begin point : rising edge of ck C ck # defined by the end of odtlcwn 4 or odtlcwn 8 vrtt _ wr vrtt _ nom
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 8 2 rev 1 . 2 0 1 / 200 9 input / output capacitance symbol parameter ddr3 - 800 ( - ac/ - ad ) ddr3 - 1066 ( - be/ - b f ) ddr3 - 1333 ( - cf/ - cg ) ddr3 - 1600 ( - d g / - dh ) units notes m in. m ax m in. m ax m in. m ax m in. m ax c io input/output capacitance (dq, dm, dqs, ??? , tdqs, ???? ) 1.5 3 1.5 3 1.5 2.5 1.5 2.3 pf 1,2,3 c ck input capacitance, ck and ck 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 pf 2,3 c dck input capacitance delta, ck and ?? 0 0.15 0 0.15 0 0.15 0 0.15 pf 2, 3,4 c ddqs input/output capacitance delta, dqs and ??? 0 0.2 0 0.2 0 0.15 0 0.15 pf 2,3,5 c i input capacitance, ctrl, add, cmd input - only pins 0.75 1.5 0.75 1.5 0.75 1.3 0.75 1.3 pf 2,3,7,8 c di_ctrl input capacitance delta, all ctrl input - only pins - 0.5 0.3 - 0.5 0.3 - 0.4 0.2 - 0.4 0.2 pf 2,3,7,8 c di_add_cmd input capacitance delta, all add/cmd input - only pins - 0.5 0.5 - 0.5 0.5 - 0.4 0.4 - 0.4 0.4 pf 2,3,9,10 c dio input/output capacitance delta, dq, dm, dqs, ??? , tdqs, ???? - 0.5 0.3 - 0.5 0.3 - 0.5 0.3 - 0.5 0 .3 pf 2,3,11 c zq input/output capacitance of zq pin - 3 - 3 - 3 - 3 pf 2,3,12 1. although the dm, tdqs and ???? pins have different functions, the loading matches dq and dqs 2. this parameter is not subject to production test. it is verified by design an d characterization. vdd=vddq=1.5v, vbias=vdd/2 and on - die termination off. 3. this parameter applies to monolithic devices only; stacked/dual - die devices are not covered here 4. absolute value of cck - c ?? 5. absolute value of cio(dqs) - cio( ??? ) 6. ci applie s to odt, ?? , cke, a0 - a1 3 , ba0 - ba2, ??? , ??? , ?? . 7. cdi_ctrl applies to odt, ?? and cke 8. cdi_ctrl=ci(ctrl) - 0.5*(ci(clk)+ci( ??? )) 9. cdi_add_cmd applies to a0 - a1 3 , ba0 - ba2, ??? , ??? and ?? 10. cdi_add_cmd=ci(add_cmd) - 0.5*(ci(clk)+ci( ??? )) 11. cdio=cio( dq,dm) - 0.5*(cio(dqs)+cio( ??? )) 12. maximum external load capacitance on zq pin: 5 pf.
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 83 rev 1 . 2 0 1 / 200 9 dd specifications and measurement conditions idd specifications symbol parameter/condition i/o ddr3 - 800 ( - ac/ - ad ) ddr3 - 1066 ( - be / - bf ) ddr3 - 1333 ( - cf/ - cg ) ddr3 - 1 600 ( - dg/ - dh ) unit idd0 operating current 0 - > one bank activate - > precharge x4 x8/x16 75 100 85 110 95 120 tbd ma idd1 operating current 1 - > one bank activate - > read - > precharge x4 x8 x16 90 115 115 100 125 135 100 135 155 tbd ma idd2p(0) precharge pow er - down current slow exit - mr0 bit a12 = 0 all 16 16 16 tbd ma idd2p(1) precharge power - down current fast exit - mr0 bit a12 = 1 all 30 30 30 tbd ma idd2n precharge standby current all 55 65 70 tbd ma idd2q precharge quiet standby current all 50 55 6 0 tbd ma idd3p active power - down current always fast exit all 35 40 45 tbd ma idd3n active standby current all 60 65 70 tbd ma idd4r operating current burst read x4/x8 x16 130 190 160 230 200 370 tbd ma idd4w operating current burst write x4/x8 x16 140 220 160 270 200 330 tbd ma idd5b burst refresh current all 230 250 270 tbd ma idd6 self - refresh current normal temperature range (0 - 85 ? c) all 14 14 14 tbd ma idd7 all bank interleave read current x4 x8 x16 250 280 300 280 300 330 330 360 400 tbd ma
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 84 rev 1 . 2 0 1 / 200 9 idd measurement conditions symbol parameter/condition idd0 operating current - one bank active - precharge current cke: high; external clock: on; tck, trc, tras: see table in the next page; cs: high between act and pre; command inputs: swit ching 1 (except for act and pre); row, column address, data i/o: switching1 (a10 low permanently); bank address: fixed (bank 0); output buffer: off 2 ; odt: disabled 3 ; active banks: one (act - pre loop); idle banks: all other; pattern example: a0 d dd dd dd d d dd dd d p0 4 (ddr3 - 800: tras=37.5ns) idd1 operating one bank active - read - precharge current cke: high; external clock: on; tck, trc, tras, trcd, cl, al: see table in the next page; cs: high between act, rd, and pre; command inputs: switching 1 (except act, rd, and pre commands); row, column address: switching1 (a10 low permanently); bank address: fixed (bank 0); data i/o: switching every clock (rd data stable during one clock cycle); floating when no burst activity; output buffer: off 2 ; odt: disabled 3 ; bur st length: bl85; active banks: one (act - rd - pre loop); idle banks: all other; pattern example: a0 d dd d r0 dd dd dd dd d p0 4 (ddr3 - 800 - 5 - 5 - 5: trcd=12.5ns). idd2n precharge standby current cke=high; external clock=on; tck: see table in the next page; cs: h igh; command inputs, row, column, bank address, data i/o: switching 1 ; output buffer: off 2 ; odt: disabled 3 ; active / idle banks: none / all. idd2p(0) precharge power - down current - (slow exit) cke=low; external clock=on; tck: see table in the next page; cs: stable; command inputs: stable; row, column / bank address: stable; data i/o: floating; output buffer: off 2 ; odt: disabled 3 ; active / idle banks: none / all. precharge power down mode: slow exit 6 (rd and odt must satisfy txpdll - al) idd2p(1) prechar ge power - down current - (fast exit) cke=low; external clock=on; tck: see table in the next page; cs: stable; command inputs, row, column, bank address: stable; data i/o: floating; output buffer: off 2 ; odt: disabled 3 ; active / idle banks: none / all. prech arge power down mode: fast exit 6(any valid command after txp) 7 idd2q precharge quiet standby current cke=high; external clock=on; tck: see table in the next page; cs=high; command inputs, row, column, bank address: stable; data i/o: floating; output buff er: off2; odt: disabled 3 ; active / idle banks: none / all. idd3n active standby current cke=high; external clock=on; tck: see table in the next page; cs=high; command inputs, row, column, bank address, data i/o: switching 1 ; output buffer: off2; odt: dis abled 3 ; active / idle banks: all / none. idd3p active power - down current cke=low; external clock=on; tck: see table in the next page; cs, command inputs, row, column, bank address: stable; data i/o: floating; output buffer: off2; odt: disabled 3 ; active / idle banks: all / none. idd4r operating burst read c urrent cke=high; external clock=on; tck, cl: see table in the next page; al: 0; cs: high between valid commands; command inputs: switching 1 (except rd commands); row, column address: switching 1 (a10: low permanently); bank address: cycling 10 ; data i/o: seamless read data burst : output data switches every clock cycle (i.e. data stable during one clock cycle); output buffer: off 2 ; odt: disabled 3 ; burst length: bl8 5 ; active / idle banks: all / none 10 ; patt ern: r0 d dd r1 d dd r2 d dd r3 d dd r4 4 idd4w operating burst write c urrent cke=high; external clock=on; tck, cl: see table in the next page; al: 0; cs: high between valid commands; command inputs: switching 1 (except wr commands); row, column address: swi tching 1 (a10: low permanently); bank address: cycling 10 ; data i/o: seamless write data burst : input data switches every clock cycle (i.e. data stable during one clock cycle); dm: l permanently; output buffer: off 2 ; odt: disabled 3 ; burst length: bl8 5 ; acti ve / idle banks: all / none 10 ; pattern: w0 d dd w1 d dd w2 d dd w3 d dd w4 4 idd5b burst refresh current cke=high; external clock=on; tck, trfc: see table in the next page; cs: high between valid commands; command inputs, row, column, bank addresses, data i/o: switching 1 ; output buffer: off 2 ; odt: disabled 3 ; active banks: refresh command every trfc=trfc(idd); idle banks: none. idd6 self - refresh current tcase=0 - 85 ? c; auto self refresh =disable; self refresh temperature range=normal 9 ; pasr: full array 11 ; c ke=low; external clock=off (ck and ck: low); cs, command inputs, row, column address, bank address, data i/o: floating; output buffer: off 2 ; odt: disabled 3 ; active banks: all (during self - refresh action); idle banks: all (between self - rerefresh actions)
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 85 rev 1 . 2 0 1 / 200 9 idd6et self - refresh current: extended temperature range tcase=0 - 95 ? c; auto self refresh =disable; self refresh temperature range=extended 9 ; pasr: full array 11 ; cke=low; external clock=off (ck and ck: low); cs, command inputs, row, column address, bank add ress, data i/o: floating; output buffer: off 2 ; odt: disabled 3 ; active banks: all (during self - refresh action); idle banks: all (between self - rerefresh actions) idd6tc auto self - refresh current tcase=0 - 95 ? c; auto self refresh =enable 8 ; self refresh tempe rature range=normal 9 ; pasr: full array 11 ; cke=low; external clock=off (ck and ck: low); cs, command inputs, row, column address, bank address, data i/o: floating; output buffer: off 2 ; odt: disabled 3 ; active banks: all (during self - refresh action); idle b anks: all (between self - rerefresh actions) idd7 operating bank interleave read current cke=high; external clock=on; tck, trc, tras, trcd, trrd, cl: see table as below; al=trcd.min - tck; cs=high between valid commands; command input: see table; row, column address: stable during deselect; bank address: cycling 10 ; data i/o: read data: output data switches every clock cycle (i.e. data stable during one clock cycle); output buffer: off 2 ;odt: disabled 3 ; burst length: bl8; active / idle banks: all 10 / none. note1: switching for address and command input signals as described in definition of switching for address and command input signals table. note2: output buffer off: set mr1 a[12] = 1 note3: odt disable: set mr1 a[9,6,2]=000 and mr2 a[10,9]=00 note4: defin ition of d and d: described in definition of switching for address and command input signals table; ax/rx/wx: activate/read/write to bank x. note5: bl8 fixed by mrs: set mr0 a[1,0]=00 note6: precharge power down mode: set mr0 a12=0/1 for slow/fast exit not e7: because it is an exit after precharge power down, the valid commands are: act, ref, mrs, enter self - refresh. note8: auto self - refresh(asr): set mr2 a6 = 0/1 to disable/enable feature note9: self - refresh temperature range (srt): set mr2 a7 = 0/1 for nor mal/extended temperature range note10: cycle banks as follows: 0,1,2,3,...,7,0,1,... note11: partial array self - refresh (pasr) disabled: set mr2 a[2,1,0] = 000
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 86 rev 1 . 2 0 1 / 200 9 for id testing the following parameters are utilized. for testing the idd parameters, the fol lowing timing parameters are used : parameter symbol ddr3 - 800 ( - ac ) d dr3 - 800 ( - ad ) unit 5 - 5 - 5 6 - 6 - 6 clock cycle time tckmin(idd) 2.5 2.5 ns cas latency cl(idd) 5 6 ck active to read or write delay trcdmin(idd) 12.5 15 ns active to active / auto - refresh command period trcmin(idd) 50 52.5 ns active to precharge command trasmin(idd) 37.5 37.5 ns precharge command period trpmin(idd) 12.5 15 ns four activate window x4/x8 tfaw(idd) 40 40 ns x16 50 50 ns active to active command period x4/x8 trrd(idd) 10 10 ns x16 10 10 ns auto - refresh to active / auto - refresh command period trfc(idd) 110 110 ns parameter symbol ddr3 - 1 066 ( - be ) ddr3 - 1 066 ( - bf ) unit 7 - 7 - 7 8 - 8 - 8 clock cycle time tckmin(idd) 1.875 1.875 ns cas latency cl(idd) 7 8 ck active to read or write delay trcdmin(idd) 13.1 25 15 ns active to active / auto - refresh command period trcmin(idd) 50.6 3 52.5 ns active to precharge command trasmin(idd) 37.5 37.5 ns precharge command period trpmin(idd) 13.1 3 15 ns four activate window x4/x8 tfaw(idd) 37.5 37.5 ns x16 50 50 ns active to active command period x4/x8 trrd(idd) 7.5 7.5 ns x16 10 10 ns auto - refresh to active / auto - refresh command period trfc(idd) 110 110 ns
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 87 rev 1 . 2 0 1 / 200 9 parameter symbol ddr3 - 1333 ( - c f ) d dr3 - 1333 ( - cg ) unit 8 - 8 - 8 9 - 9 - 9 clock cycle time tckmin(idd) 1.5 1.5 ns active to read or write delay trcdmin(idd) 12 13.5 ns active to active / auto - refresh command period trcmin(idd) 48 49.5 ns active to precharge command trasmin(idd) 36 36 ns precharge command period trpmin(idd) 12 13.5 ns four activate window x4/x8 tfaw(idd) 30 30 ns x16 45 45 ns active to active command period x4/x8 trrd(idd) 6 6 ns x16 7.5 7.5 ns auto - refresh to active / auto - refresh command period trfc(idd) 110 110 ns parameter symbol ddr3 - 1600 ( - dg ) ddr3 - 1 600 ( - dh ) unit 9 - 9 - 9 10 - 10 - 10 clock cycle time tckmin(idd) 1.25 1.25 ns active to read or write delay trcdmin(idd) 11.25 12.5 ns active to active / auto - refresh command period trcmin(idd) 46.25 47.5 ns active to precharge command trasmin(idd) 35 35 ns precharge command period tr pmin(idd) 11.25 12.5 ns four activate window x4/x8 tfaw(idd) 30 30 ns x16 40 40 ns active to active command period x4/x8 trrd(idd) 6 6 ns x16 7.5 7.5 ns auto - refresh to active / auto - refresh command period trfc(idd) 110 110 ns
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 88 rev 1 . 2 0 1 / 200 9 definition of swi tching for address and command input signals switching for address (row, column) and command signals (cs, ras, cas, we) is defined as: address (row, column) if not otherwise mentioned the inputs are stable at high or low during 4 clocks and change then to the opposite value (e.g. ax ax ax ax ?? ?? ?? ?? ax ax ax ax please see each iddx definition for details bank address if not otherwise mentioned the bank addresses should be switched like the row/column address - please see each iddx for details command (cs, ras, cas, we) define d = { ?? , ??? , ??? , ?? } := {high, low, low, low} define d = { ??? , ??? , ??? , ?? } := {high, high, high, high} define command backgr ound pattern = d d ? ? d d ? ? d d ? ? .... if other commands are necessary (e.g. act for idd0 or read for idd4r), the background pattern command is substituted by the respective ?? , ??? , ??? , ?? levels of the necessary command. see e ach iddx definition for details . standard speed bins speed bin ddr3 - 800 ddr3 - 1066 unit cl - nrcd - nrp 5 - 5 - 5 ( - ac) 6 - 6 - 6 ( - ad) 7 - 7 - 7 ( - be) 8 - 8 - 8 ( - bf) parameter symbol min max min max min max min max. internal read command to first data taa 12.5 20 15 20 13.125 20 15 20 ns a ct to internal read or write delay time trcd 12.5 - 15 - 13.125 - 15 - ns pre command period trp 12.5 - 15 - 13.125 - 15 - ns act to act or ref command period trc 50 - 52.2 - 50.625 - 52.5 - ns act to pre command period tras 37.5 9*trefi 37.5 9*trefi 37 .5 9*trefi 37.5 9*trefi ns cl= 5 ; cwl =5 tck(avg) 2.5 3.3 reserved reserved reserved ns cl=6; cwl =5 tck(avg) 2.5 3.3 2.5 3.3 2.5 3.3 2.5 3.3 ns cl=7; cwl =6 tck(avg) reserved reserved 1.875 <2.5 reserved ns cl=8; cwl =6 tck(avg) reserved reserved 1.875 <2.5 1.875 <2.5 ns supported cl settings 5,6 6 6,7,8 6,8 nck supported cwl settings 5 5 5,6 5,6 nck
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 89 rev 1 . 2 0 1 / 200 9 speed bin ddr3 - 1333 ddr3 - 1 600 unit cl - nrcd - nrp 8 - 8 - 8 ( - cf) 9 - 9 - 9 ( - cg) 9 - 9 - 9 ( - dg ) 10 - 10 - 10 ( - dh) parameter symbol min max min max min max min max. internal read command to first data taa 12 20 13.5 20 1 1. 25 20 1 2. 5 20 ns act to inte rnal read or write delay time trcd 12 - 13.5 - 1 1 . 25 - 1 2. 5 - ns pre command period trp 12 - 13.5 - 1 1 . 25 - 1 2. 5 - ns act to act or ref command period trc 48 - 49.5 - 4 6 . 25 - 47 .5 - ns act to pre command period tras 36 9*trefi 36 9*trefi 3 5 9*trefi 35 9 *trefi ns cl= 5 ; cwl =5 tck(avg) 2.5 3.3 reserved 2.5 3.3 2.5 3.3 ns cl=6; cwl =5 tck(avg) 2.5 3.3 2.5 3.3 2.5 3.3 2.5 3.3 ns cl=6; cwl = 6 tck(avg) reserved reserved 1.875 <2.5 reserved ns cl=7; cwl =6 tck(avg) 1.875 <2.5 reserved 1.875 <2.5 1.875 <2.5 ns cl=8; cwl =6 tck(avg) 1.875 <2.5 1.875 <2.5 1.875 <2.5 1.875 <2.5 ns cl=8; cwl = 7 tck(avg) 1.5 < 1.875 reserved 1.5 < 1.875 reserved ns cl=9; cwl =7 tck(avg) 1.5 < 1.875 1.5 < 1.875 1.25 <1.5 1.25 <1.5 ns cl=9; cwl = 8 tck(avg) reserved reserved 1.25 <1. 5 reserved ns cl10; cwl=7 tck(avg) 1 1.5 1 < 1.875 1 1.5 1 < 1.875 1.5 < 1.875 1.5 < 1.875 ns cl10; cwl= 8 tck(avg) reserved reserved 1.25 <1.5 1.25 <1.5 ns cl11; cwl=8 tck(avg) reserved reserved 1 1.25 1 <1.5 1 1.25 1 <1.5 ns supported cl settings 5,6 ,7,8, 9 6 ,8,9 6,7,8 ,9,10 6,8 ,10,11 nck supported cwl settings 5 ,6,7 5 ,6,7 5,6,7,8 5,6,7,8 nck note: 1. optional
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 90 rev 1 . 2 0 1 / 200 9 electrical characteristics & ac timing timing parameter by speed bin unit min max min max tck(dll_off) minimum clock cycle time (dll off mode) 8 - 8 - ns tck(avg) average clock period(refer to "standard speed bins") tch(avg) average high pulse width 0.47 0.53 0.47 0.53 tck(avg) tcl(avg) average low pulse width 0.47 0.53 0.47 0.53 tck(avg) tck(abs) absolute clock period tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max ps tch(abs) absolute high pulse width 0.43 - 0.43 - tck(avg) tcl(abs) absolute low pulse width 0.43 - 0.43 - tck(avg) jit(per) clock period jitter -100 100 -90 90 ps tjit(per,lck) clock period jitter during dll locking period -90 90 -80 80 ps tjit(cc) cycle to clcyle period jitter ps tjit(cc,lck) cycle to cycle period jitter ps terr(2per) cumulative error accross 2 cycles -147 147 -132 132 ps terr(3per) cumulative error accross 3 cycles -175 175 -157 157 ps terr(4per) cumulative error accross 4cycles -194 194 -175 175 ps terr(5per) cumulative error accross 5cycles -209 209 -188 188 ps terr(6per) cumulative error accross 6 cycles -222 222 -200 200 ps terr(7per) cumulative error accross 7 cycles -232 232 -209 209 ps terr(8per) cumulative error accross 8 cycles -241 241 -217 217 ps terr(9per) cumulative error accross 9 cycles -249 249 -224 224 ps terr(10per) cumulative error accross 10 cycles -257 257 -231 231 ps terr(11per) cumulative error accross 11 cycles -263 263 -237 237 ps terr(12per) cumulative error accross 12 cycles -269 269 -242 242 ps terr(nper) cumulative error accross n=13,14,..,49,50 cycles terr(npr)min = (1+ 0.68in(n)) * tjit(per)min terr(npr)max = (1+ 0.68in(n)) * tjit(per)max terr(npr)min = (1+ 0.68in(n)) * tjit(per)min terr(npr)max = (1+ 0.68in(n)) * tjit(per)max ps data timing tdqsq dqs, dqs to dq skew per group, per access - 200 - 150 ps tqh dq output hold time from dqs, dqs 0.38 - 0.38 - tck(avg) tlz(dq) dq low-impedence time from ck / ?? -800 400 -600 300 ps thz(dq) dq high-impedence time from ck / ?? - 400 - 300 ps tds(base) data setup time to dqs, dqs referenced to vih(ac)/ vil(ac) levels 75 25 ps tdh(base) data hold time to dqs, dqs referenced to vih(dc)/ vil(dc) levels 150 100 ps tdipw dq and dm input pulse width for each input 600 490 ps data strobe timing trpre dqs, dqs differential read preamble 0.9 note 19 0.9 note 19 tck(avg) trpst dqs, dqs differential read postamble 0.3 note 11 0.3 note 11 tck(avg) tqsh dqs, dqs differential output high time 0.38 - 0.38 - tck(avg) tqsl dqs, dqs differential output low time 0.38 - 0.38 - tck(avg) twpre dqs, dqs differential write preamble 0.9 - 0.9 - tck(avg) twpst dqs, dqs differential write postamble 0.3 - 0.3 - tck(avg) tdqsck dqs, dqs rising edge output access time from rising ck, ?? -400 400 -300 300 ps tlz(dqs) dqs, dqs low-impedance time (referenced from rl-1) -800 400 -600 300 ps thz(dqs) dqs, dqs high-impedance time (referenced from rl+bl/2) - 400 - 300 ps tdqsl dqs, dqs differential input low pulse width 0.4 0.6 0.4 0.6 tck(avg) tdqsh dqs, dqs differential input high pulse width 0.4 0.6 0.4 0.6 tck(avg) tdqss dqs, dqs rising edge to ck, ?? rising edge -0.25 0.25 -0.25 0.25 tck(avg) tdss dqs, dqs falling edge setup time to ck, ?? rising edge 0.2 - 0.2 - tck(avg) tdsh dqs, dqs falling edge hold time to ck, ?? rising edge 0.2 - 0.2 - tck(avg) 180 160 ddr3-800 (-ac/-ad) ddr3-1066 (-be/-bf) 200 180 clock timing refer to "standard speed bins) symbol parameter
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 91 rev 1 . 2 0 1 / 200 9 unit min max min max command and address timing tdllk dll locking time 512 - 512 - nck trtp internal read command to precharge command delay max(4nck, 7.5ns) - max(4nck, 7.5ns) - twtr delay from start of internal write transaction to internal read command max(4nck, 7.5ns) - max(4nck, 7.5ns) - twr write recovery time 15 - 15 - ns tmrd mode register set command cycle time 4 - 4 - nck tmod mode register set command update delay max(12nck, 15ns) - max(12nck, 15ns) - tccd cas to cas command delay 4 - 4 - nck tdal auto precharge write recovery + precharge time nck tmprr end of mpr read burst to msr for mpr (exit) 1 - 1 - nck tras active to precharge command period refer to "standard speed bins" trrd active to active command period (1k page size - x4/x8) max(4nck, 10ns) - max(4nck, 7.5ns) - trrd active to active command period (2k page size -x16) max(4nck, 10ns) - max(4nck, 10ns) - tfaw four activate window (1k page size - x4/x8) 40 - 37.5 - ns tfaw four activate window (2k page size - x16) 50 - 50 - ns tis(base) command and address setup time to ck, ?? referenced vih(ac) / vil(ac) levels 200 125 ps tih(base) command and address hold time from ck, ?? referenced vih(ac) / vil(ac) levels 275 200 ps tis(base) ac150 commad and address setup time to ck, ?? referenced to vih(ac) / vil(ac) levels - - - - ps calibration timing tzqinit power-up and reset calibration time 512 - 512 - nck tzqoper normal operation full calibration time 256 - 256 - nck tzqcs normal operation short calibration time 64 - 64 - nck reset timing txpr exit reset from cke high to a valid command max(5nck, trfc(min) +10ns) - max(5nck, trfc(min) +10ns) - self refreshtimings txs exit self refresh to commands not requiring a locked dll max(5nck, trfc(min) +10ns) - max(5nck, trfc(min) +10ns) - txsdll exit self refresh to commands requiring a locked dll tdllk(min) - tdllk(min) - nck tckesr minimum cke low width for self refresh entry to exit timing tcke(min)+1n ck - tcke(min)+1nc k - tcksre valid clock requirement after self refresh entry (sre) or power down entry (pde) max(5nck, 10ns) - max(5nck, 10ns) - tcksrx valid clock requirement before self refresh exit(srx) or power-down exit (pdx) or reset exit max(5nck, 10ns) - max(5nck, 10ns) - power down timings txp exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll max(3nck, 7.5ns) - max(3nck, 7.5ns) - txpdll exit precharge power down with dll frozen to commands requiring a locked dll max(10nck, 24ns) - max(10nck, 24ns) - tcke cke minimm pulse width max(3nck, 7.5ns) - max(3nck, 5.625ns) - tcpded command pass disable delay 1 - 1 - nck tpd power down entry to exit timing tcke(min) 9trefi tcke(min) 9trefi tactpden timing of act command to power down entry 1 - 1 - nck tprpden timing of pre or prea command to power down entry 1 - 1 - nck symbol parameter ddr3-800 (-ac/-ad) ddr3-1066 (-be/-bf) wr + roundup (trp/tck(avg)) wr + roundup (trp/tck(avg))
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 92 rev 1 . 2 0 1 / 200 9 unit min max min max twrpden timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) wl + 4 + (twr/tck(avg)) - wl + 4 + (twr/tck(avg)) - nck twrapden timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) wl + 4 + wr + 1 - wl + 4 + wr + 1 - nck twrpden timing of wr command to power down entry (bc4mrs) wl + 2 + (twr/tck(avg)) - wl + 2 + (twr/tck(avg)) - nck twrapden timing of wra command to power down entry (bc4mrs) wl + 2 + wr + 1 - wl + 2 + wr + 1 - nck trefpden timing of ref command to power down entry 1 - 1 - nck tmrspden timing of mrs command to power down entry tmod(min) - tmod(min) - odt timings todth4 odt high time without write command or with write command and bc4 4 - 4 - nck todth8 odt high time without write command oand bl8 6 - 6 - nck taonpd asynchronous rtt turn-on delay (power-down with dll frozen) 1 9 1 9 ns taofpd asynchronous rtt turn-off delay (power down with dll frozen) 1 9 1 9 ns taon rtt turn-on -400 400 -300 300 ps taof rtt_nom and rtt_wr turn-off time from odtloff reference 0.3 0.7 0.3 0.7 tck(avg) tadc rtt dynamic change skew 0.3 0.7 0.3 0.7 tck(avg) write leveling timings twlmrd first dqs/dqs rising edge after write leveling mode is programmed 40 - 40 - nck twldqsen dqs/dqs delay after write leveling mode is porgramed 25 - 25 - nck twls write leveling setup time from rising ck, ck crossing to rising dqs, dqs crossing 325 - 245 - ps twlh write leveling hold time from rising dqs, dqs crossing to rising ck, ck crossing 325 - 245 - ps twlo write leveling output delay 0 9 0 9 ns twloe write levleing output error 0 2 0 2 ns trfc ref command to act or ref command time ns trefi average period refresh interval (0c t case 85c) us trefi average period refresh interval (85c 1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 93 rev 1 . 2 0 1 / 200 9 unit min max min max tck(dll_off) minimum clock cycle time (dll off mode) 8 - 8 -8 ns tck(avg) average clock period(refer to "standard speed bins") tch(avg) average high pulse width 0.47 0.53 0.47 0.53 tck(avg) tcl(avg) average low pulse width 0.47 0.53 0.47 0.53 tck(avg) tck(abs) absolute clock period tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max ps tch(abs) absolute high pulse width 0.43 - 0.43 - tck(avg) tcl(abs) absolute low pulse width 0.43 - 0.43 - tck(avg) jit(per) clock period jitter -80 80 -70 70 ps tjit(per,lck) clock period jitter during dll locking period -70 70 -60 60 ps tjit(cc) cycle to clcyle period jitter ps tjit(cc,lck) cycle to cycle period jitter ps terr(2per) cumulative error accross 2 cycles -118 118 -103 103 ps terr(3per) cumulative error accross 3 cycles -140 140 -122 122 ps terr(4per) cumulative error accross 4cycles -155 155 -136 136 ps terr(5per) cumulative error accross 5cycles -168 168 -147 147 ps terr(6per) cumulative error accross 6 cycles -177 177 -155 155 ps terr(7per) cumulative error accross 7 cycles -186 186 -163 163 ps terr(8per) cumulative error accross 8 cycles -193 193 -169 169 ps terr(9per) cumulative error accross 9 cycles -200 200 -175 175 ps terr(10per) cumulative error accross 10 cycles -205 205 -180 180 ps terr(11per) cumulative error accross 11 cycles -210 210 -184 184 ps terr(12per) cumulative error accross 12 cycles -215 215 -188 188 ps terr(nper) cumulative error accross n=13,14,..,49,50 cycles terr(npr)min = (1+ 0.68in(n)) * tjit(per)min terr(npr)max = (1+ 0.68in(n)) * tjit(per)max terr(npr)min = (1+ 0.68in(n)) * tjit(per)min terr(npr)max = (1+ 0.68in(n)) * tjit(per)max ps data timing tdqsq dqs, dqs to dq skew per group, per access - 125 - 100 ps tqh dq output hold time from dqs, dqs 0.38 - 0.38 - tck(avg) tlz(dq) dq low-impedence time from ck / ?? -500 250 -500 225 ps thz(dq) dq high-impedence time from ck / ?? - 250 - 225 ps tds(base) data setup time to dqs, dqs referenced to vih(ac)/ vil(ac) levels 30 10 ps tdh(base) data hold time to dqs, dqs referenced to vih(dc)/ vil(dc) levels 65 45 ps tdipw dq and dm input pulse width for each input 400 360 ps data strobe timing trpre dqs, dqs differential read preamble 0.9 note 19 0.9 note 19 tck(avg) trpst dqs, dqs differential read postamble 0.3 note 11 0.3 note 11 tck(avg) tqsh dqs, dqs differential output high time 0.4 - 0.4 - tck(avg) tqsl dqs, dqs differential output low time 0.4 - 0.4 - tck(avg) twpre dqs, dqs differential write preamble 0.9 - 0.9 - tck(avg) twpst dqs, dqs differential write postamble 0.3 - 0.3 - tck(avg) tdqsck dqs, dqs rising edge output access time from rising ck, ?? -255 255 -255 255 ps tlz(dqs) dqs, dqs low-impedance time (referenced from rl-1) -500 250 -450 225 ps thz(dqs) dqs, dqs high-impedance time (referenced from rl+bl/2) - 250 - 225 ps tdqsl dqs, dqs differential input low pulse width 0.4 0.6 0.4 0.6 tck(avg) tdqsh dqs, dqs differential input high pulse width 0.4 0.6 0.4 0.6 tck(avg) tdqss dqs, dqs rising edge to ck, ?? rising edge -0.25 0.25 -0.25 0.25 tck(avg) tdss dqs, dqs falling edge setup time to ck, ?? rising edge 0.2 - 0.2 - tck(avg) tdsh dqs, dqs falling edge hold time to ck, ?? rising edge 0.2 - 0.2 - tck(avg) symbol parameter ddr3-1333 (-cf/-cg) 160 refer to "standard speed bins) 140 ddr3-1600 (-dg/-dh) clock timing refer to "standard speed bins" 140 120
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 94 rev 1 . 2 0 1 / 200 9 unit min max min max command and address timing tdllk dll locking time 512 - 512 - nck trtp internal read command to precharge command delay max(4nck, 7.5ns) - max(4nck, 7.5ns) - twtr delay from start of internal write transaction to internal read command max(4nck, 7.5ns) - max(4nck, 7.5ns) - twr write recovery time 15 - 15 - ns tmrd mode register set command cycle time 4 - 4 - nck tmod mode register set command update delay max(12nck, 15ns) - max(12nck, 15ns) - tccd cas to cas command delay 4 - 4 - nck tdal auto precharge write recovery + precharge time nck tmprr end of mpr read burst to msr for mpr (exit) 1 - 1 - nck tras active to precharge command period refer to "standard speed bins" trrd active to active command period (1k page size - x4/x8) max(4nck, 6ns) - max(4nck, 6ns) - trrd active to active command period (2k page size -x16) max(4nck, 7.5ns) - max(4nck, 7.5ns) - tfaw four activate window (1k page size - x4/x8) 30 - 30 - ns tfaw four activate window (2k page size - x16) 45 - 40 - ns tis(base) command and address setup time to ck, ?? referenced vih(ac) / vil(ac) levels 65 45 ps tih(base) command and address hold time from ck, ?? referenced vih(ac) / vil(ac) levels 140 120 ps tis(base) ac150 commad and address setup time to ck, ?? referenced to vih(ac) / vil(ac) levels 65+125 45+125 ps calibration timing tzqinit power-up and reset calibration time 512 - 512 - nck tzqoper normal operation full calibration time 256 - 256 - nck tzqcs normal operation short calibration time 64 - 64 - nck reset timing txpr exit reset from cke high to a valid command max(5nck, trfc(min) +10ns) - max(5nck, trfc(min) +10ns) - self refreshtimings txs exit self refresh to commands not requiring a locked dll max(5nck, trfc(min) +10ns) - max(5nck, trfc(min) +10ns) - txsdll exit self refresh to commands requiring a locked dll tdllk(min) - tdllk(min) - nck tckesr minimum cke low width for self refresh entry to exit timing tcke(min)+1nck - tcke(min)+1nc k - tcksre valid clock requirement after self refresh entry (sre) or power down entry (pde) max(5nck, 10ns) - max(5nck, 10ns) - tcksrx valid clock requirement before self refresh exit(srx) or power-down exit (pdx) or reset exit max(5nck, 10ns) - max(5nck, 10ns) - power down timings txp exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll max(3nck, 6ns) - max(3nck, 6ns) - txpdll exit precharge power down with dll frozen to commands requiring a locked dll max(10nck, 24ns) - max(10nck, 24ns) - tcke cke minimm pulse width max(3nck, 5.625ns) - max(3nck, 5.625ns) - tcpded command pass disable delay 1 - 1 - nck tpd power down entry to exit timing tcke(min) 9trefi tcke(min) 9trefi tactpden timing of act command to power down entry 1 - 1 - nck tprpden timing of pre or prea command to power down entry 1 - 1 - nck symbol parameter ddr3-1333 (-cf/-cg) ddr3-1600 (-dg/-dh) wr + roundup (trp/tck(avg)) refer to standard speed bin"
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 95 rev 1 . 2 0 1 / 200 9 unit min max min max twrpden timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) wl + 4 + (twr/tck(avg)) - wl + 4 + (twr/tck(avg)) - nck twrapden timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) wl + 4 + wr + 1 - wl + 4 + wr + 1 - nck twrpden timing of wr command to power down entry (bc4mrs) wl + 2 + (twr/tck(avg)) - wl + 2 + (twr/tck(avg)) - nck twrapden timing of wra command to power down entry (bc4mrs) wl + 2 + wr + 1 - wl + 2 + wr + 1 - nck trefpden timing of ref command to power down entry 1 - 1 - nck tmrspden timing of mrs command to power down entry tmod(min) - tmod(min) - odt timings todth4 odt high time without write command or with write command and bc4 4 - 4 - nck todth8 odt high time without write command oand bl8 6 - 6 - nck taonpd asynchronous rtt turn-on delay (power-down with dll frozen) 1 9 1 9 ns taofpd asynchronous rtt turn-off delay (power down with dll frozen) 1 9 1 9 ns taon rtt turn-on -250 250 -225 225 ps taof rtt_nom and rtt_wr turn-off time from odtloff reference 0.3 0.7 0.3 0.7 tck(avg) tadc rtt dynamic change skew 0.3 0.7 0.3 0.7 tck(avg) write leveling timings twlmrd first dqs/dqs rising edge after write leveling mode is programmed 40 - 40 - nck twldqsen dqs/dqs delay after write leveling mode is porgramed 25 - 25 - nck twls write leveling setup time from rising ck, ck crossing to rising dqs, dqs crossing 195 - tbd - ps twlh write leveling hold time from rising dqs, dqs crossing to rising ck, ck crossing 195 - tbd - ps twlo write leveling output delay 0 9 0 7.5 ns twloe write levleing output error 0 2 0 2 ns trfc ref command to act or ref command time ns trefi average period refresh interval (0c t case 85c) us ddr3-1333 (-cf/-cg) 7.8 110 ddr3-1600 (-dg/-dh) 110 7.8 symbol parameter
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 96 rev 1 . 2 0 1 / 200 9 jitter notes specific note a unit tck(avg) represents the actual tck(avg) of the input clock under operation. unit nck represents one clock cycle of the input clock, counting the actual clock edges. ex) tmrd=4 [nck] means; if one mode register set command is regis tered at tm, anther mode register set comma nd may be registered at tm+4, even if (tm+4 - tm) is 4 x tck(avg) + terr(4per), min. specific note b these parameters are measured from a command/address signal (cke, cs, ras, cas, we, odt, ba0, a0, a1, etc) tran sition edge to its respective clock signal ( ck/ck) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the com mand/address. that is, these parameters should be met whether clock jitter is present or not. specific note c these parameters are measured from a data strobe signal (dqs(l/u), dqs(l/u)) crossing to its respective clock signal (ck, ck) crossing. the spec values are not affected by the amount of clock ji tter applied (i.e. tjit(per), tjit(cc), etc), as these are relative to the clock signal crossing. that is, these parameters should be met whether clock jitter is present or not. specific note d these parameters are measured from a data signal (dm(l/u), dq( l/u)0, dq(l/u)1, etc.) transition edge to its respective data strobe signal (dqs(l/u), dqs(l/u)) crossing. specific note e for these parameters, the ddr3 sdram device supports tnparam [nck] = ru{tparam[ns] / tck(avg)[ns]}, which is in clock cycles, assumin g all input clock jitter specifications are satisfied. for example, the device will support tnrp = ru{trp/tck(avg)}, which is in clock cycles, if all input clock jitter specifications are met. this means: for ddr3 - 800 6 - 6 - 6, of which trp = 15ns, the device will support tnrp = ru{trp/tck(avg)} = 6, as long as the input clock jitter specifications are met, i.e. precharge command at tm and active command at tm+6 is valid even if (tm+6 - tm) is less than 15ns due to input clock jitter. specific note e when the d evice is operated with input clock jitter, this parameter needs to be derated by the actual terr(mper), act of the input clock, where 2 <= m <=12. (output derating are relative to the sdram input clock.) for example, if the measured jitter into a ddr3 - 800 sdram has terr(mper),act,min = - 172ps and terr(mper),act,max = 193ps, then tdqsck,min(derated) = tdqsck,min - terr(mper),act,max = - 400ps - 193ps = - 593ps and tdqsck,max(derated) = tdqsck,max - terr(mper),act,min = 400ps + 172ps = 572ps. similarly, tlz(dq) for ddr3 - 800 derates to tlz(dq),min(derated) = - 800ps - 193ps = - 993ps and tlz(dq),max(derated) = 400ps + 172ps = 572ps. (caution on the min/max usage!) note that terr(mper),act,min is the minimum measured value of terr(nper) where 2 <= n <= 12, and terr( mper),act,max is the maximum measured value of terr(nper) where 2 <= n <= 12. specific note g when the device is operated with input clock jitter, this parameter needs to be derated by the actual tjit(per),act of the in put clock. (output deratings are rela tive to the sdram input clock.) for example, if the measured jitter into a ddr3 - 800 sdram has tck(avg),act=2500ps, tjit(per),act,min = - 72ps and tjit(per),act,max = 93ps, then trpre,min(derated) = trpre,min + tjit(per),act,min = 0.9 x tck(avg),act + tjit(p er),act,min = 0.9 x 2500ps - 72ps = 2178ps. similarly, tqh,min(derated) = tqh,min + tjit(per),act,min = 0.38 x tck(avg),act + tjit(per),act,min = 0.38 x 2500ps - 72ps = 878ps. (caution on the min/max usage!)
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 97 rev 1 . 2 0 1 / 200 9 timing parameter notes 1. actual value dependent u pon measurement level definitions which are tbd. 2. commands requiring a locked dll are: read ( and rap) are synchronous odt commands. 3. the max values are system dependent. 4. wr as programmed in mode register. 5. value must be rouned - up to next higher integer valu e. 6. there is no maximum cycle time limit besides the need to satisfy the refresh interval, trefi. 7. for definition of rtt - on time taon see timing parameters. 8. for definition of rtt - off time taof see timing parameters. 9. twr is defined in ns, for calculation of twrpden it is necessary to round up twr / tck to the next integer. 10. wr in clock cycles are programmed in mr0. 11. the maximum read postamble is bonded by tdqsck(min) plus tqsh(min) on the left side and thz(dqs)max on the right side. 12. output timing deratings a re relative to the sdram input clock. when the device is operated with input clock jitter, this parameter needs to be derated by tbd. 13. value is only valid for ron34. 14. single ended signal parameter. 15. trefi depends on toper. 16. tis(base) and tih(base) values are for 1v/ns cmd/add single - ended slew rate and 2v/ns ck, ck differential slew rate. note for dq and dm signals, vref(dc)=vrefdq(dc). for input only pins except reset, vref(dc)=vrefca(dc). 17. tds(base) and tdh(base) values are for 1v/ns dq single - ended slew rat e and 2v/ns dqs, dqs differential slew rate. note for dq and dm signals, vref(dc)=vrefdq(dc). for input only pins except reset, vref(dc)=vrefca(dc). 18. start of internal write transaction is defined as follows: for bl8 (fixed by mrs and on - the - fly): rising c lock edge 4 clock cycles after wl. for bc4 (on - the - fly): rising clock edge 4 clock cycles after wl. for bc4 (fixed by mrs): rising clock edge 2 clock cycles after wl. 19. the maximum preamble is bound by tlz(dqs)max on the left side and tdqsck(max) on the righ t side. 20. cke is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progr ess, but power - down idd spec will not be applied until finishing those operations. 21. although cke is allowed to be registered low after a refresh command once trefpden(min) is satisfied, there are cases where additional time such as txpdll(min) is also required. 22. defined between end of mpr read burst and mrs which reloads mpr or disables mpr function.
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 98 rev 1 . 2 0 1 / 200 9 23. one zqcs command can effe ctively correct a minimum of 0.5% (zqcorrection) of ron and rtt impedance error within 64 nck for all speed bins assuming the maximum sensitivities specified in the output driver voltage and temperature sensitivity an d odt voltage and temperature sensit ivity tables. the appropriate interval between zqcs commands can be determined from these tables and other application - specific parameters. one method for calculating the interval between zqcs commands, given the temperature (tdriftrate) and voltage (vdri ft rate) drift rates that the sdram is subject to in the application, is illustrated. the interval could be defined by the following formula : zqcorrection / [(tsens x tdriftrate) + (vsens x vdriftrate)] where tsens = max(drttdt, drondtm) and vsens = max(dr ttdv, drondvm) define the sdram temperature and voltage sensitivities. for example, if tsens = 1.5%/c, vsens = 0.15%/mv, tdriftrate = 1 c/sec and vdriftrate = 15mv/sec, then the interval between zqcs commands is calculated as 0.5 / [(1.5x1)+(0.15x15)] = 0 .133 ~ 128ms 24. n = from 13 cycles to 50 cycles. this row defines 38 parameters. 25. tch(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge . 26. tcl(abs) is the absolute instantaneous clock low pu lse width, as measured from one falling edge to the following rising edge. 27. the tis(base) ac150 specifications are adjusted from the tis(base) specification by adding an additional 100ps of derating to accommodate for the lower altemate threshold of 150mv a nd another 25ps to account for the earlier reference point [(175mv - 150mv) / 1v/ns].
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 99 rev 1 . 2 0 1 / 200 9 address / command setup, hold, and derating for all input signals the total tis (setup time) and tih (hold time) required is calculated by adding the data sheet tis(ba se) and tih(base) and tih(base) value to the delta tis and delta tih derating value respectively. example: tis (total setup time) = tis(base) + delta tis setup (tis) nominal slew rate for a rising signal is defined as the slew rate between the last cross ing of vref(dc) and the first crossing of vih(ac)min. setup (tis) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref( dc) and the first crossing of vil(ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded ?vref(dc) to ac region?, use nominal slew rate for derating value. if the actual signal is later than the nominal slew rate line anywhere between shad ed ?vref(dc) to ac region?, the slew rate of the tangent line to th e actual signal from the ac level to dc level is used for derating value. hold (tih) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the first crossing of vref(dc). hold (tih) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc)min and the first crossing of vref(dc). if the actual signal is always later than the nominal slew rate line between shaded ?dc to vref(d c) region?, use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line any where between shaded ?dc to vref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to vref(dc) level is used for derati ng value. for a valid transition the input signal has to remain above/below vih/il(ac) for some time tvac. although for slow slew rates the t otal setup time might be negative (i.e. a valid input signal will not have reached vih/il(ac) at the time of the rising clock tra nsition) a valid input signal is still required to complete the transition and reach vih/il(ac). add/cmd setup and hold base - values for 1v/ns unit [ps] ddr3 - 800 ( - ac/ - ad) ddr3 - 1066 ( - be / - bf ) ddr3 - 1333 ( - cf/ - cg) ddr3 - 1 600 ( - cf/ - cg) reference tis(base) 20 0 125 65 45 vih/l(ac) tih(base) 275 200 140 120 vih/l(dc) tih(base) ac150 - 65+125 45 +125 vih/l(dc) note: 1. (ac/dc referenced for 1v/ns dq - slew rate and 2v/ns dqs slew rate. 2. the tis(base) ac150 specifications are adjusted from the tis(base) specifi cation by adding an additional 100ps of derating to accommodate for the lower alternate threshold of 150mv and another 25ps to account for the earlier reference point [(175mv - 150mv) / 1v/ns].
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 100 rev 1 . 2 0 1 / 200 9 required time tvac above vih(ac) { below vil(ac)} for valid transition slew rate [v/ns] tvac@175mv [ps] tvac@175mv [ps] min max min max >2.0 75 - 175 - 2 57 - 170 - 1.5 50 - 167 - 1 38 - 163 - 0.9 34 - 162 - 0.8 29 - 161 - 0.7 22 - 159 - 0.6 13 - 155 - 0.5 0 - 150 - <0.5 0 - 150 - tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih 2.0 88 50 88 50 88 50 96 58 104 66 112 74 120 84 128 100 1.5 59 34 59 34 59 34 67 42 75 50 83 58 91 68 99 84 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 -2 -4 -2 -4 -2 -4 6 4 14 12 22 20 30 30 38 46 0.8 -6 -10 -6 -10 -6 -10 2 -2 10 6 18 14 26 24 34 40 0.7 -11 -16 -11 -16 -11 -16 -3 -8 5 0 13 8 21 18 29 34 0.6 -17 -26 -17 -26 -17 -26 -9 -18 -1 -10 7 -2 15 8 23 24 0.5 -35 -40 -35 -40 -35 -40 -27 -32 -19 -24 -11 -16 -2 -6 5 10 0.4 -62 -60 -62 -60 -62 -60 -54 -52 -46 -44 -38 -36 -30 -26 -22 -10 tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih 2.0 75 50 75 50 75 50 83 58 91 66 99 74 107 84 115 100 1.5 50 34 50 34 50 34 58 42 66 50 74 58 82 68 90 84 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 0 -4 0 -4 0 -4 8 4 16 12 24 20 32 30 40 46 0.8 0 -10 0 -10 0 -10 8 -2 16 6 24 14 32 24 40 40 0.7 0 -16 0 -16 0 -16 8 -8 16 0 24 8 32 18 40 34 0.6 -1 -26 -1 -26 -1 -26 7 -18 15 -10 23 -2 31 8 39 24 0.5 -10 -40 -10 -40 -10 -40 -2 -32 6 -24 14 -16 22 -6 30 10 0.4 -25 -60 -25 -60 -25 -60 -17 -52 -9 -44 -1 -36 7 -26 15 -10 1.2 v/ns 1.0 v/ns 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns derating values ddr3-1333/1600 tis/tih - ac/dc based - alternate ac150 threshold tis, tih derating in [ps] ac/dc based alternate ac150 threshold -> vih(ac)=vref(dc)+150mv, vil(ac)=vref(dc)-150mv ck, ?? cmd/add slew rate v/ns derating values ddr3-800/1066/1333/1600 tis/tih - ac/dc based tis, tih derating in [ps] ac/dc based alternate ac150 threshold -> vih(ac)=vref(dc)+175mv, vil(ac)=vref(dc)-175mv ck, ?? 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns cmd/add slew rate v/ns
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 101 rev 1 . 2 0 1 / 200 9 data setup, hold, and slew rate derating for all input signals the total tds (setup time) and tdh (hold time) required is calculated by adding the data sheet tdh(base ) and tdh(base) value to the delta tds and delta tdh derating value respectively. e xample: tds (total setup time) = tds(base) + delta tds setup (tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the f irst crossing of vih(ac)min. setup (tds) nominal slew rate for a falling si gnal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vil(ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded ?vref (dc) to ac region?, use nominal slew rate for derating v alue. if the actual signal is later than the nominal slew rate line anywhere between shaded ?vref(dc) to ac region?, the slew rate of the tangent line to the actual signal from the ac level to dc level is used for der ating value. hold (tdh) nominal slew r ate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the first crossing of vref(dc). hold (tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc)min and the fi rst crossing of vref(dc). if the actual signal is always later than the nominal slew rate line between shaded ?dc level to vref(dc) region?, use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew ra te line anywhere between shaded ?dc to vref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to vref(dc) le vel is used for derating value. for a valid transition the input signal has to remain above/below vih/il(ac) for some time tvac. although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached vih/il(a c) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach vih/il(a c). for slew rates in between the values listed in the following tables, the derating values may be obtained by linear interpolat ion. these values are typically not subject to production test. they are verified by design and characterization. data setup and hold base - values unit [ps] ddr3 - 800 ( - ac/ - ad) ddr3 - 1066 ( - be / - bf ) ddr3 - 1333 ( - cf/ - cg) ddr3 - 1600 ( - dg/ - dh) reference tds(base) 75 25 - 10 vih/l(ac) tdh(base) 150 100 65 vih/l(dc) note: ac/dc referenced for 1v/ns dq - slew rate and 2v/ns dqs slew ra te
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 102 rev 1 . 2 0 1 / 200 9 derating values ddr3 - 800/ 1066 tds/tdh - ac/dc based derating values ddr3 - 1333/ 1 600 tds/tdh - ac/dc based required time tvac above vih(ac) {below vil(ac)} for valid transition slew rate [v/ns] ddr3 - 800/1066 ddr3 - 1333/1600 min max min max >2.0 75 - 1 75 - 2 57 - 170 - 1.5 50 - 167 - 1 38 - 163 - 0.9 34 - 162 - 0.8 29 - 161 - 0.7 22 - 159 - 0.6 13 - 155 - 0.5 0 - 150 - <0.5 0 - 150 - d tds d tdh d tds d tdh d tds d tdh d tds d tdh d tds d tdh d tds d tdh d tds d tdh d tds d tdh 2 88 50 88 50 88 50 - - - - - - - - - - 1.5 59 34 59 34 59 34 67 42 - - - - - - - - 1 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - -2 -4 -2 -4 6 4 14 12 22 20 - - - - 0.8 - - - - -6 -10 2 -2 10 6 18 14 26 24 - - 0.7 - - - - - - -3 -8 5 0 13 8 21 18 29 34 0.6 - - - - - - - - -1 -10 7 -2 15 8 23 24 0.5 - - - - - - - - - - -11 -16 -2 -6 5 10 0.4 - - - - - - - - - - - - -30 -26 -22 -10 dqs, dqs differential slew rate delta tds, delta tdh derating in ac/dc based 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.0 v/ns 1.2 v/ns dq slew rate (v/ns) 4.0 v/ns 3.0 v/ns d tds d tdh d tds d tdh d tds d tdh d tds d tdh d tds d tdh d tds d tdh d tds d tdh d tds d tdh 2 75 50 75 50 75 50 - - - - - - - - - - 1.5 50 34 50 34 50 34 58 42 - - - - - - - - 1 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - 0 -4 0 -4 8 4 16 12 24 20 - - - - 0.8 - - - - 0 -10 8 -2 16 6 24 14 32 24 - - 0.7 - - - - - - 8 -8 16 0 24 8 32 18 40 34 0.6 - - - - - - - - 15 -10 23 -2 31 8 39 24 0.5 - - - - - - - - - - 14 -16 22 -6 30 10 0.4 - - - - - - - - - - - - 7 -26 15 -10 dq slew rate (v/ns) 4.0 v/ns 3.0 v/ns dqs, dqs differential slew rate delta tds, delta tdh derating in ac/dc based 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.0 v/ns 1.2 v/ns
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 103 rev 1 . 2 0 1 / 200 9 package dimensions (x4 /x8 ; 78 balls; 0.8mmx0.8mm pitch; bga dual die package) 0 . 8 6 . 4 0 . 8 9 . 0 + / - 0 . 1 1 3 . 0 + / - 0 . 1 p i n a 1 i n d e x p i n a 1 i n d e x m i n . 0 . 3 0 m a x . 0 . 4 0 m a x . 1 . 3 9 t o p v i e w b o t t o m v i e w 9 . 6 m i n . 0 . 4 2 m a x . 0 . 5 2 7 8 b a l l s u n i t s : m m
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 104 rev 1 . 2 0 1 / 200 9 package dimensions (x 16 ; 96 balls; 0.8mmx0.8mm pitch; bga dual die package) 0 . 8 6 . 4 9 . 0 +/ - 0 . 1 1 3 . 0 + / - 0 . 1 pin a 1 index pin a 1 index min . 0 . 30 max . 0 . 40 max . 1 . 39 top view bottom view 1 2 min . 0 . 42 max . 0 . 52 78 balls units : mm 0 . 8
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 105 rev 1 . 2 0 1 / 200 9 revision log rev date modification 0.1 0 4 /2008 preliminary release 0.2 05/2008 updated simplified state diagram (p.7) updated mr2 definition (p.18) updated timing details of write leveling sequence (p.30) updated timing details of write leveling exit (p.31) added refresh command (p.50) updated mrs command to power down entry (p.54) updated sync odt timing example (p.57) updated synchronous to asynchronous odt mode transition during power - down entry (p.63) updated sync to async transition during precharge power down (with dll frozen) (p.63) updated ac and dc logic input levels for single - ended signals(p.67) added vref tolerances (p.68) added def inition of differential ac - swing and time above ac - level (p.69) updated single - ended levels table (p.70) updated cross point voltage for differential input signals. (p.70) replaced single - ended input slew rate definition table input nominal slew rate def inition for single - ended signals figure input slew rate for input setup time and data setup time section input slew rate for input hold time and data hold time section with reference to existing definitions of single - ended signals section (p.102) updated d ifferential input slew rate definition (p. 71) updated idd measurement conditions(p.87/88) updated input/output capacitance table (p.85) updated ddr3 - 1333 standard speed pins table (p.90) updated timing parameters by speed bin (p.90) updated and reordered jitter notes (p.99) updated timing parameter notes 11 and 19 for read trpre and trpst 1.0 06/2008 added idd currents official release 1.1 08/2008 added tdipw data on timing parameters on (p. 90 & p. 93) add ddr2 - 1600 - cl9/cl10 item spec. 1.2 01/2009 upd ated idd4r/idd4w burst read/write typo ( p.83)
1gb ddr3 sdram a - die nt5cb 256m4 an / nt5cb128m8an / nt5cb64m16ap 106 rev 1 . 2 0 1 / 200 9 n anya technology corporation. all rights reserved. printed in taiwan, r.o.c., 2006 the following are trademarks of nanya technology corporation in r.o.c, or other countries , or both. nanya and nanya logo other company, product and service names may be trademarks or service marks of others. nanya technology corporation (ntc) reserves the right to make changes without notice. ntc warrants performance of its semiconductor pro ducts and related software to the specifications applicable at the time of sale in accordance with ntc?s standard warranty. testing and other quality control techniques are utilize to the extent ntc deems necessary to support this warranty. specific testin g of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (critical applications). ntc semiconductor products are not designed, intend, authorized, or warranted to be suitable for use in life - support applications, devices or systems or other critical applications. inclusion of ntc products in such applic ations is understood to be fully at the risk of the customer. use of ntc products in such applications requires the written approval of an appropriate ntc officer. question concerning potential risk applications should be directed to ntc through a local sa les office. in order to minimize risks associated with the customer?s applications, adequate design and operating safeguards should be provided by customer to minimize the inherent or procedural hazards.ntc assumes no liability of applications assistance, customer product design, software performance, or infringement of patents or services described herein. nor does ntc warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other i ntellectual property right of ntc covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. nanya technology corporation hwa ya technology park 669, fu hsing 3rd rd., kueishan, taoy uan, taiwan, r.o.c. the nanya technology corporation home page can be found at http: \ \ www.nanya.com ?

▲Up To Search▲

Price & Availability of NT5CB64M16AP-CF

	To Download NT5CB64M16AP-CF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .